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Change subject: mb/google/fatcat: Add support for soldered-down memory
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
I will incorporate similar change for Intel RVP. Thanks!
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Change subject: util/spd_tools: Add Intel Panther Lake (PTL) platform
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Patch Set 1: Code-Review+2
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Change subject: mb/google/brox/var/jubilant: Add SAR sensor SX9324
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Patch Set 8: Code-Review+2
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Change subject: mb/google/brox/var/lotso: Enable wifi sar
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Patch Set 2: Code-Review+2
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Change subject: intel/alderlake: Drop redundant Client/AlderLake* FSP paths
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83826/comment/49b4aee3_f43498ff?us… :
PS1, Line 413: default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && !SOC_INTEL_RAPTORLAKE
> > > Either way we would need additional infrastructure to track which boards
> > > shouldn't get the update. And after all, this is the *main* branch. So we
> > > should really ask, is it worth the hassle?
> >
> > I'm leaving this upto you if you think it's okay to enforce all ADL device to switch to converged FW (with RPL).
> >
> > I have shared my side of the story where forcing ADL to RPL migration involves validation cost and it should leave upto the platform owners if they are okay to offer RPL FSP for their older ADL device or not.
>
> I don't see us enforcing anything.
I'm not saying that you/your CL is enforcing anything rather I'm saying Intel is enforcing ADL only devices with coreboot/FSP to switch to RPL FSP (this will bring additional cost of validation).
> There is no policy that I know of that says
> platform owners have to validate the upstream main branch. And if anybody wants
> to go through and add additional infrastructure to track more FSP versions, I
> wouldn't stop them (in fact, I've argued in the past that one submodule pointer
> per platform or even per board might be better).
>
> Subrata, please help me understand the problem you see better to avoid future
> friction:
> * Do you / does Google validate the upstream main branch with configs that include `CONFIG_FSP_USE_REPO=y`?
We don't use FSP repo for blobs and we compile the binary from source. What I have shared in my experience working on converged FSP where some of the ADL device broken and the fixed with later RPL FSP releases.
> * Do you know about anybody else who does?
> * Does your validation differ for minor FSP updates (that we can have with any submodule pointer update) vs. switching from ADL to converged RPL?
The validation/debugging cost includes feature, functionality and stability brokenness issue seen on few ADL devices with RPL FSP.
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Change subject: commonlib/bsd: Add strnlen() and strlen() functions
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/libc/string.c:
https://review.coreboot.org/c/coreboot/+/83830/comment/d88515a2_685329cc?us… :
PS1, Line 71: /* NULL and empty strings have length 0. */
: if (!str)
: return 0;
You don't have this NULL check in the commonlib implementation. If you are unlucky a payload actually calls these functions with a possible NULL value. That would break the payloads if they did depend on that fact before this patch.
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Change subject: soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
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Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/var/teliks: Configure TPM IRQ for teliks
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Patch Set 1:
This change is ready for review.
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