Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83813?usp=email )
Change subject: soc/amd/picasso/Makefile: move PSP_NVRAM_[BASE,SIZE]
......................................................................
soc/amd/picasso/Makefile: move PSP_NVRAM_[BASE,SIZE]
Move PSP_NVRAM_BASE and PSP_NVRAM_SIZE from the BIOS directory table
items to the PSP Directory Table items, since the corresponding region
will be referenced by the PSP directory table and not the BIOS directory
table.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83813
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/soc/amd/picasso/Makefile.mk
1 file changed, 5 insertions(+), 5 deletions(-)
Approvals:
Marshall Dawson: Looks good to me, approved
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk
index b65d1c8..7545bb2 100644
--- a/src/soc/amd/picasso/Makefile.mk
+++ b/src/soc/amd/picasso/Makefile.mk
@@ -83,6 +83,11 @@
OPT_PSP_LOAD_S0I3_FW="--load-s0i3"
endif
+# type = 0x04
+# The flashmap section used for this is expected to be named PSP_NVRAM
+PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START)
+PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE)
+
# type = 0x3a
ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
@@ -91,11 +96,6 @@
# BIOS Directory Table items - proper ordering is managed by amdfwtool
#
-# type = 0x4
-# The flashmap section used for this is expected to be named PSP_NVRAM
-PSP_NVRAM_BASE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_START)
-PSP_NVRAM_SIZE=$(call get_fmap_value,FMAP_SECTION_PSP_NVRAM_SIZE)
-
# type = 0x7
# RSA 2048 signature
#ifeq ($(CONFIG_PSP_PLATFORM_SECURE_BOOT),y)
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iff7568ea05c701ecd346cc7590cf93b091ff31a2
Gerrit-Change-Number: 83813
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83812?usp=email )
Change subject: util/amdfwtool: add support to specify RPMC NVRAM region
......................................................................
util/amdfwtool: add support to specify RPMC NVRAM region
Add support to specify the base and size of the replay-protected
monotonic counter (RPMC) non-volatile storage area in the SPI flash. A
later patch will use this to tell amdfwtool about the location and size
of the corresponding FMAP section.
This code is ported from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Idafa7d9bf64125bcabd9b47e77147bcffee739e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83812
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/opts.c
2 files changed, 18 insertions(+), 1 deletion(-)
Approvals:
Martin Roth: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Matt DeVillier: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 1dac476..1fe9923 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1011,7 +1011,8 @@
pspdir->entries[count].addr = fw_table[i].other;
pspdir->entries[count].address_mode = 0;
count++;
- } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
+ } else if (fw_table[i].type == AMD_FW_PSP_NVRAM ||
+ fw_table[i].type == AMD_RPMC_NVRAM) {
if (fw_table[i].filename == NULL) {
if (fw_table[i].size == 0)
continue;
diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c
index 511ffd0..62bbc97 100644
--- a/util/amdfwtool/opts.c
+++ b/util/amdfwtool/opts.c
@@ -68,6 +68,8 @@
LONGOPT_BIOS_SIG = 259,
LONGOPT_NVRAM_BASE = 260,
LONGOPT_NVRAM_SIZE = 261,
+ LONGOPT_RPMC_NVRAM_BASE = 262,
+ LONGOPT_RPMC_NVRAM_SIZE = 263,
};
static const char optstring[] = {AMDFW_OPT_CONFIG, ':',
@@ -87,6 +89,8 @@
{"nvram", required_argument, 0, AMDFW_OPT_NVRAM },
{"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE },
{"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE },
+ {"rpmc-nvram-base", required_argument, 0, LONGOPT_RPMC_NVRAM_BASE },
+ {"rpmc-nvram-size", required_argument, 0, LONGOPT_RPMC_NVRAM_SIZE },
{"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE },
{"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK },
{"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST },
@@ -150,6 +154,8 @@
printf("--token-unlock Set token unlock\n");
printf("--nvram-base <HEX_VAL> Base address of nvram\n");
printf("--nvram-size <HEX_VAL> Size of nvram\n");
+ printf("--rpmc-nvram-base <HEX_VAL> Base address of RPMC nvram\n");
+ printf("--rpmc-nvram-size <HEX_VAL> Size of RPMC nvram\n");
printf("--whitelist Set if there is a whitelist\n");
printf("--use-pspsecureos Set if psp secure OS is needed\n");
printf("--load-mp2-fw Set if load MP2 firmware\n");
@@ -577,6 +583,16 @@
register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg);
sub = instance = 0;
break;
+ case LONGOPT_RPMC_NVRAM_BASE:
+ /* PSP RPMC NV base */
+ register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, optarg, 0);
+ sub = instance = 0;
+ break;
+ case LONGOPT_RPMC_NVRAM_SIZE:
+ /* PSP RPMC NV size */
+ register_amd_psp_fw_addr(AMD_RPMC_NVRAM, sub, 0, optarg);
+ sub = instance = 0;
+ break;
case AMDFW_OPT_CONFIG:
cb_config->config = optarg;
break;
--
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jack Lai, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun, Tyler Wang.
YH Lin has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/83791?usp=email )
Change subject: mb/google/rex/karis: Set PCIE WLAN bluetooth companion device
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Please use a separate CL to remove the setting in cnvi_wifi.
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