Attention is currently required from: Felix Singer, Nico Huber, Torsten Schenk.
Martin L Roth has posted comments on this change by Torsten Schenk. ( https://review.coreboot.org/c/coreboot/+/83379?usp=email )
Change subject: Makefile: unexport CFLAGS
......................................................................
Patch Set 1:
(1 comment)
File Makefile:
https://review.coreboot.org/c/coreboot/+/83379/comment/5f0f00d2_1fbadeb8?us… :
PS1, Line 7: unexport CFLAGS
> Should we unexport LDFLAGS too? Anything else?
I think this is the wrong way to go about this.
coreboot shouldn't be using a bare CFLAGS variable in its own builds, so it shouldn't be getting set to need to be unexported.
This one should be updated to set it's own cflags:
util/marvell/doimage_mv/Makefile.mk:CFLAGS = -g -O1 -I./../inc -DMV_CPU_LE -I $(TOP)/src/commonlib/bsd/include
This one isn't a problem since it's a part of a rule and setting cflags just before calling make.
src/security/vboot/Makefile.mk: CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \
Same here:
src/arch/arm64/Makefile.mk: CFLAGS="$(BL31_CFLAGS)"
Also, if it's leaking into another build, just clear CFLAGS when doing the other build.
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5fe75095aec620ef1bcdb5506dc7d29e482697a1
Gerrit-Change-Number: 83379
Gerrit-PatchSet: 1
Gerrit-Owner: Torsten Schenk
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-CC: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
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Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83697?usp=email )
Change subject: MAINTAINERS: Add Maximilian Brune to RISC-V
......................................................................
MAINTAINERS: Add Maximilian Brune to RISC-V
I also add myself as the Maintainer for the SiFive boards, since I
happen to have both of them and I also ported the HiFive Unmatched to
coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic0b8e1053c9f5007e29e997c1ff21ff4a496aea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83697
Reviewed-by: ron minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M MAINTAINERS
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
Felix Singer: Looks good to me, approved
ron minnich: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/MAINTAINERS b/MAINTAINERS
index 4371d11..edf8561 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -604,7 +604,8 @@
SIFIVE MAINBOARDS
-S: Orphan
+M: Maximilian Brune <maximilian.brune(a)9elements.com>
+S: Maintained
F: src/mainboard/sifive/
@@ -665,6 +666,7 @@
RISC-V ARCHITECTURE
M: Ronald Minnich <rminnich(a)gmail.com>
+M: Maximilian Brune <maximilian.brune(a)9elements.com>
R: Philipp Hug <philipp(a)hug.cx>
S: Maintained
F: src/arch/riscv/
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Attention is currently required from: Maximilian Brune.
Felix Singer has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83697?usp=email )
Change subject: MAINTAINERS: Add Maximilian Brune to RISC-V
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
Details:
- Skeleton files to compile google/fatcat mainboard.
BUG=b:348678529
TEST=Build verified on with using PTL SOC and google/fatcat mainboard.
Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83732
Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
6 files changed, 481 insertions(+), 0 deletions(-)
Approvals:
Ravishankar Sarawadi: Looks good to me, but someone else must approve
Jamie Ryu: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Ronak Kanabar: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
new file mode 100644
index 0000000..ec19ec1
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
@@ -0,0 +1,61 @@
+/** @file
+ Header file for Firmware Version Information
+
+ @copyright
+ Copyright (c) 2015 - 2024, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
+ http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.p…
+
+**/
+
+#ifndef __FIRMWARE_VERSION_INFO_H__
+#define __FIRMWARE_VERSION_INFO_H__
+
+#include <IndustryStandard/SmBios.h>
+
+#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info"
+#define INTEL_FVI_SMBIOS_TYPE 0xDD
+
+#pragma pack(1)
+
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} INTEL_FIRMWARE_VERSION;
+
+///
+/// Firmware Version Info (FVI) Structure
+///
+typedef struct {
+ SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name
+ SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String
+ INTEL_FIRMWARE_VERSION Version; ///< Firmware version
+} INTEL_FIRMWARE_VERSION_INFO;
+
+///
+/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure
+///
+typedef struct {
+ SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
+ UINT8 Count; ///< Number of FVI entries in this structure
+ INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
+} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h
new file mode 100644
index 0000000..d27815c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h
@@ -0,0 +1,82 @@
+/** @file
+
+ Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef _FSP_PRODUCER_DATA_HEADER_H_
+#define _FSP_PRODUCER_DATA_HEADER_H_
+
+#include <Guid/FspHeaderFile.h>
+
+#define BUILD_TIME_STAMP_SIZE 12
+
+//
+// FSP Header Data structure from FspHeader driver.
+//
+#pragma pack(1)
+///
+/// FSP Producer Data Subtype - 1
+///
+typedef struct {
+ ///
+ /// Byte 0x00: Length of this FSP producer data type record.
+ ///
+ UINT16 Length;
+ ///
+ /// Byte 0x02: FSP producer data type.
+ ///
+ UINT8 Type;
+ ///
+ /// Byte 0x03: Revision of this FSP producer data type.
+ ///
+ UINT8 Revision;
+ ///
+ /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image.
+ ///
+ UINT32 RcVersion;
+ ///
+ /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM".
+ ///
+ UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE];
+} FSP_PRODUCER_DATA_TYPE1;
+
+///
+/// FSP Producer Data Subtype - 2
+///
+typedef struct {
+ ///
+ /// Byte 0x00: Length of this FSP producer data type record.
+ ///
+ UINT16 Length;
+ ///
+ /// Byte 0x02: FSP producer data type.
+ ///
+ UINT8 Type;
+ ///
+ /// Byte 0x03: Revision of this FSP producer data type.
+ ///
+ UINT8 Revision;
+ ///
+ /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image.
+ ///
+ UINT8 MrcVersion [4];
+} FSP_PRODUCER_DATA_TYPE2;
+
+
+typedef struct {
+ FSP_INFO_HEADER FspInfoHeader;
+ FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader;
+ FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1;
+ FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2;
+ FSP_PATCH_TABLE FspPatchTable;
+} FSP_PRODUCER_DATA_TABLES;
+#pragma pack()
+
+#endif // _FSP_PRODUCER_DATA_HEADER_H
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h
new file mode 100644
index 0000000..9661285
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C5450 /* 'PTLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5450 /* 'PTLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C5450 /* 'PTLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
new file mode 100644
index 0000000..4c98fa8
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -0,0 +1,76 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+/** FSP M Configuration
+**/
+typedef struct {
+ /* Placeholder for FSP_M_CONFIG UPDs */
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH2_UPD FspmArchUpd;
+
+/** Offset 0x0060
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0060
+**/
+ UINT8 UnusedUpdSpace4[6];
+
+/** Offset 0x0066
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
new file mode 100644
index 0000000..938c283
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -0,0 +1,94 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+/** FSP S Configuration
+**/
+typedef struct {
+ /* Placeholder for FSP_S_CONFIG UPDs */
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPS_ARCH2_UPD FspsArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0040
+**/
+ UINT8 UnusedUpdSpace1[6];
+
+/** Offset 0x0046
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
new file mode 100644
index 0000000..e010348
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -0,0 +1,120 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ @copyright
+ Copyright (c) 1999 - 2024, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+@par Specification Reference:
+**/
+
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+
+#pragma pack (push, 1)
+
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
+ #ifndef INT32_MAX
+ #define INT32_MAX (0x7FFFFFFF)
+ #endif //INT32_MAX
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif //__MRC_BOOT_MODE__
+
+/**
+ Memory Info Data Hob
+**/
+typedef struct {
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+**/
+typedef struct {
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83786?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: device/pci_ids: Add new Intel PTL device IDs for Tracehub
......................................................................
device/pci_ids: Add new Intel PTL device IDs for Tracehub
This patch adds new North Peak PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the tracehub driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Boot to OS using PTL Silicon, verify if above 4GB IMR region is
reserved.
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83786
Reviewed-by: Anil Kumar K <anil.kumar.k(a)intel.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/tracehub/tracehub.c
2 files changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Anil Kumar K: Looks good to me, but someone else must approve
Subrata Banik: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index b721bb4..481bf20 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4902,6 +4902,8 @@
/* Intel Trace Hub */
#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24
#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f
+#define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424
+#define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324
/* Intel Ethernet Controller device Ids */
#define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
index 480e9ef..ba56c4c 100644
--- a/src/soc/intel/common/block/tracehub/tracehub.c
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -42,6 +42,8 @@
};
static const unsigned short pci_device_ids[] = {
+ PCI_DID_INTEL_PTL_H_TRACEHUB,
+ PCI_DID_INTEL_PTL_U_H_TRACEHUB,
PCI_DID_INTEL_MTL_TRACEHUB,
PCI_DID_INTEL_RPL_TRACEHUB,
0
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
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Gerrit-Change-Id: Ifa1a0a57c504e06d686e7e0826547251b456cc8b
Gerrit-Change-Number: 83786
Gerrit-PatchSet: 5
Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>