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Change subject: soc/intel/adl: update libgx config to a generic eSOL config
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83841/comment/0caf543c_ac937fd8?us… :
PS1, Line 7: update libgx config to a generic eSOL config
:
: This patch updates the early libgfx init configuration used for
: alderlake SOC with a generic Chrome early sign of life configuration.
> we are binding early GFX initialization with a use case Kconfig (CHROMEOS_ENABLE_ESOL) rather the un […]
Acknowledged
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign-of-life config option when
libgfx or uGOP is enabled for early graphics initialization.
BUG=b:352651132
TEST=Able to build google/rex and google/tivviks
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/vendorcode/google/chromeos/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/27
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Change subject: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
......................................................................
soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a FSP
uGOP eSOL config (FSP_UGOP_EARLY_SIGN_OF_LIFE) and a generic Chrome
eSOL config(CHROMEOS_ENABLE_ESOL).
This patch does not change the binary or the system behaviour.
BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83769/22
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Change subject: soc/intel/adl: update libgx config to a generic eSOL config
......................................................................
soc/intel/adl: update libgx config to a generic eSOL config
This patch updates the early libgfx init config
(MAINBOARD_HAS_EARLY_LIBGFXINIT) used for alderlake SOC with a
generic Chrome early sign of life config(CHROMEOS_ENABLE_ESOL).
This patch does not change the binary or the system behaviour. and is
only meant to bind the early GFX initialization with a generic eSOL
Kconfig.
BUG=b:352651132
TEST=Able to build google/tivviks and checked the config in output
Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/alderlake/romstage/ux.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/83841/2
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Change subject: soc/intel/xeon_sp/gnr: Remove VPD from GNR Kconfig
......................................................................
Patch Set 1: Code-Review+2
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83764?usp=email )
Change subject: mb/lenovo/t520: Add USB port config into devicetree
......................................................................
mb/lenovo/t520: Add USB port config into devicetree
Devicetree for lenovo/520 is missing USB ports config, hence they
don't work. This change introduces USB port config.
Tests performed:
- Can select a boot media using a USB keyboard from any port.
- Can boot from each port except usb@1:1.1.
- Measured read speed from a thumb drive on each port 24.5-28.9 MiB/s.
Change-Id: I96dba153a563e0e290b96b837fdca39d7598ef17
Signed-off-by: PuFF1k <exopuf(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83764
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---
M src/mainboard/lenovo/t520/devicetree.cb
1 file changed, 18 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin L Roth: Looks good to me, approved
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 5edb63e..c404df2 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -58,6 +58,24 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
+ # OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
+ register "usb_port_config" = "{
+ {1, 1, 0}, /* P0: system port 4, OC0 */
+ {1, 1, 1}, /* P1: system port 2 (EHCI debug), OC 1 */
+ {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */
+ {1, 0, -1}, /* P3: WWAN, no OC */
+ {1, 0, -1}, /* P4: smartcard, no OC */
+ {1, 1, -1}, /* P5: ExpressCard, no OC */
+ {0, 0, -1}, /* P6: empty */
+ {0, 0, -1}, /* P7: empty */
+ {1, 1, 4}, /* P8: system port 3, OC4*/
+ {1, 1, 5}, /* P9: system port 1 (EHCI debug), OC 5 */
+ {1, 0, -1}, /* P10: fingerprint reader, no OC */
+ {1, 0, -1}, /* P11: bluetooth, no OC. */
+ {1, 1, -1}, /* P12: docking, no OC */
+ {1, 1, -1} /* P13: camera (LCD), no OC */
+ }"
+
device ref mei1 on end
device ref mei2 off end
device ref me_ide_r off end
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Change subject: mb/lenovo/t520: Add USB port config into devicetree
......................................................................
Patch Set 4: Code-Review+2
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83764/comment/2eabafda_3049f35b?us… :
PS2, Line 2: PuFF1k
> If possible, it’d be great if you used your full name.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83764/comment/53fd4aa4_95c23489?us… :
PS2, Line 11: This change introduces USB port config.
> No need to break the line above?
Done
https://review.coreboot.org/c/coreboot/+/83764/comment/243f2a8d_e282efcd?us… :
PS2, Line 12:
> Tested how? Put a USB storage device in each port? Did you do any speed tests?
Done
File src/mainboard/lenovo/t520/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83764/comment/9a57b467_58ab99bc?us… :
PS2, Line 77: }"
> One indentation too much?
Done
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Change subject: tree: Remove duplicated <arch/mmio.h>
......................................................................
Patch Set 5: Code-Review+2
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Change subject: azalia: Get rid of "return {-1,0}
......................................................................
Patch Set 6: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83503/comment/63eecfea_ab2b8f3b?us… :
PS2, Line 9: Modern C uses {true,false}
> No. Please see https://doc.coreboot.org/contributing/coding_style. […]
Done
File src/device/azalia_device.c:
https://review.coreboot.org/c/coreboot/+/83503/comment/4f54d826_352ddbf4?us… :
PS5, Line 56: if (azalia_exit_reset(base) == CB_ERR)
> You should still test cb_errs for failure with `< 0` or `!= CB_SUCCESS`, unless you're really only l […]
Done
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