coreboot-gerrit August 2024

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[S] Change in coreboot[main]: util/cbfstool/cbfs-payload-linux: Do not compress bzImage
by Nico Huber (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Angel Pons, Felix Singer, Julius Werner, Lean Sheng Tan, Maximilian Brune. Nico Huber has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83615?usp=email ) Change subject: util/cbfstool/cbfs-payload-linux: Do not compress bzImage ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File util/cbfstool/cbfs-payload-linux.c: https://review.coreboot.org/c/coreboot/+/83615/comment/5a22fde4_ed2bbeb5?us… : PS4, Line 190: > I did that before, but I need the `algo` parameter in `bzp_output_segment` because I need to set the […] It's still a binary decission: Compress with `algo` or don't compress. So you could boil it down to a boolean parameter. -- To view, visit https://review.coreboot.org/c/coreboot/+/83615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I022982667515ce721d98af534414d9e336b5f35a Gerrit-Change-Number: 83615 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 09 Aug 2024 16:52:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add SAR sensor SX9324
by Felix Held (Code Review) 09 Aug '24

09 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83779?usp=email ) Change subject: mb/google/brox/var/jubilant: Add SAR sensor SX9324 ...................................................................... mb/google/brox/var/jubilant: Add SAR sensor SX9324 Add SAR Sensor SX9324 for WWAN: - Apply DRIVERS_I2C_SX9324 - Config GPP_H19 for IRQ - Add SX9324 registers settings based on tuning value from SEMTECH. Refer to datasheet: https://chromeos.google.com/partner/dlm/avl/component/3624/ BUG=b:345327104 TEST=Build and verify on jubilant Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83779 Reviewed-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/variants/jubilant/gpio.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb 3 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kenneth Chan: Looks good to me, approved David Wu: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 567c663..5c44afc 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -88,6 +88,7 @@ select BOARD_GOOGLE_BASEBOARD_BROX select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_ALC1015 + select DRIVERS_I2C_SX9324 select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS if BOARD_GOOGLE_BROX_COMMON diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c index 0b7ea77..0540cd1 100644 --- a/src/mainboard/google/brox/variants/jubilant/gpio.c +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -31,6 +31,8 @@ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_H23, 1, LOCK_CONFIG), + /* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC_LOCK(GPP_H19, NONE, LEVEL, NONE, LOCK_CONFIG), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR (active high) */ PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG), diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 51a0816..ca23c11 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -404,6 +404,29 @@ register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)" device generic 0 on end end + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "ph0_pin" = "{1, 2, 2}" + register "ph1_pin" = "{2, 1, 2}" + register "ph2_pin" = "{2, 2, 1}" + register "ph3_pin" = "{2, 1, 1}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "2" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe DB_USB DB_1A_LTE + end + end end device ref gspi1 on chip drivers/spi/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/83779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I629117f20ca513dc0c8eaa91744ad33e162ba4bb Gerrit-Change-Number: 83779 Gerrit-PatchSet: 9 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: region: Introduce region_create() functions
by Nico Huber (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Andrey Petrov, Felix Held, Felix Singer, Julius Werner, Jérémy Compostella, Martin L Roth, Maximilian Brune, Ronak Kanabar. Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79905?usp=email ) Change subject: region: Introduce region_create() functions ...................................................................... Patch Set 9: (2 comments) Patchset: PS9: LGTM File util/cbfstool/cse_serger.c: https://review.coreboot.org/c/coreboot/+/79905/comment/90c88077_44d68b48?us… : PS8, Line 828: strtoul > might be worth pointing out this additional change in the commit message. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Aug 2024 16:29:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: region: Introduce region_create() functions
by Nico Huber (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Andrey Petrov, Felix Held, Felix Singer, Julius Werner, Jérémy Compostella, Martin L Roth, Maximilian Brune, Nico Huber, Ronak Kanabar. Hello Andrey Petrov, Felix Held, Julius Werner, Jérémy Compostella, Martin L Roth, Maximilian Brune, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79905?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Code-Review+2 by Julius Werner, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) Change subject: region: Introduce region_create() functions ...................................................................... region: Introduce region_create() functions We introduce two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). This fixes potential overflows in region_overlap() checks in SMI handlers, where we would wrongfully report MMIO as *not* overlapping SMRAM. Also, two cases of strtol() in parse_region() (cbfstool), where the results were implicitly converted to `size_t`, are replaced with the unsigned strtoul(). FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Ticket: https://ticket.coreboot.org/issues/522 Found-by: Vadim Zaliva <lord(a)digamma.ai> Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/commonlib/include/commonlib/region.h M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/intel/fsp1_1/fsp_report.c M src/drivers/intel/fsp2_0/fspt_report.c M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/cpu/x86/smm.h M src/lib/fmap.c M src/soc/qualcomm/common/qclib.c M util/cbfstool/cbfstool.c M util/cbfstool/cse_serger.c 12 files changed, 95 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/79905/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable wifi sar
by Karthik Ramasubramanian (Code Review) 09 Aug '24

09 Aug '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83793?usp=email ) Change subject: mb/google/brox/var/lotso: Enable wifi sar ...................................................................... mb/google/brox/var/lotso: Enable wifi sar wifi.SetTXPower test fail, so enable wifi sar. BUG=b:351698478 TEST=emerge-brox coreboot Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83793 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jian Tong: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 5044695..567c663 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -76,6 +76,7 @@ config BOARD_GOOGLE_LOTSO select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS config BOARD_GOOGLE_GREENBAYUPOC -- To view, visit https://review.coreboot.org/c/coreboot/+/83793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibf5425e72eddc45e376ef4e2d077180dab502200 Gerrit-Change-Number: 83793 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: vc/intel/raptorlake: Update header files from 4435_00 to 5045_00
by Karthik Ramasubramanian (Code Review) 09 Aug '24

09 Aug '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83653?usp=email ) Change subject: vc/intel/raptorlake: Update header files from 4435_00 to 5045_00 ...................................................................... vc/intel/raptorlake: Update header files from 4435_00 to 5045_00 Update header files for FSP for Raptor Lake refresh platform to version 5045_00, previous version being 4435_00. FSPM: 1. Add IgdGsm2Size UPD 2. Comment added for Offset 0x0AB6 FSPS: 1. Add CepEnable UPD 2. Offset size updated for UPD ReservedCpuPostMemProduction 2. Comment added for Offset 0x104C MemInfoHob: 1. Structure updated BUG=b:355384183 Kit:https://www.intel.com/content/www/us/en/secure/design/confidential/ software-kits/kit-details.html?kitId=815173 Cq-Depend: chrome-internal:7554984 Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h 2 files changed, 17 insertions(+), 7 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h index 83241ef..f43cbb5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h @@ -1091,9 +1091,12 @@ **/ UINT8 SaVoltageMode; -/** Offset 0x029B +/** Offset 0x029B - Internal Graphics Data Stolen Memory GSM2 + Size of memory preallocated for internal graphics GSM2. + 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB, + 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation **/ - UINT8 Rsvd07; + UINT8 IgdGsm2Size; /** Offset 0x029C - SA/Uncore Voltage Override The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override @@ -3794,7 +3797,7 @@ **/ UINT8 CpuPcieRpSlotImplemented[4]; -/** Offset 0x0AB6 +/** Offset 0x0AB6 - Ppr Run Once Enable PPR Run Once 0:Disable, <b>1:Enable<b> 0:Disable, 1:Enable **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h index 1fe07e4..df64965 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2024, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -1778,11 +1778,17 @@ **/ UINT32 PsysCriticalThreshold; -/** Offset 0x06E0 - ReservedCpuPostMemProduction +/** Offset 0x06E0 - CepEnable + Enable or Disable Cep (Current Excursion Protection) Support. + 1: Enable, 0: Disable +**/ + UINT8 CepEnable[5]; + +/** Offset 0x06E5 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS **/ - UINT8 ReservedCpuPostMemProduction[11]; + UINT8 ReservedCpuPostMemProduction[6]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -4294,7 +4300,8 @@ **/ UINT32 ThcHidFlags[2]; -/** Offset 0x104C +/** Offset 0x104C - Force LTR Override + Force LTR Override. **/ UINT8 CpuPcieRpTestForceLtrOverride[4]; -- To view, visit https://review.coreboot.org/c/coreboot/+/83653?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80cccb6aaa8f3a97d860a1e7908bfac0435b1aec Gerrit-Change-Number: 83653 Gerrit-PatchSet: 3 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/riven: Add G2 touchscreen support
by Felix Held (Code Review) 09 Aug '24

09 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83823?usp=email ) Change subject: mb/google/nissa/var/riven: Add G2 touchscreen support ...................................................................... mb/google/nissa/var/riven: Add G2 touchscreen support This change adds the necessary configuration for the G2 Touchscreen(GTCH7503) device, connected to I2C bus 40. It includes settings for: * HID descriptor * Device description * IRQ configuration * Detection * Reset and enable GPIOs with their respective delays * Power resource handling * HID descriptor register offset BUG=b:350844195 TEST=emerge-nissa coreboot boot with G2 TS, make sure G2 TS is functional. Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83823 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/riven/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index 301d72a..411277f 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -255,6 +255,20 @@ register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2 Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" -- To view, visit https://review.coreboot.org/c/coreboot/+/83823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If17367cd62eb69a1237efe4aa3ca1a0c9640ba4c Gerrit-Change-Number: 83823 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/trulo: Enable EC MKBP device
by Felix Held (Code Review) 09 Aug '24

09 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83819?usp=email ) Change subject: mb/google/trulo: Enable EC MKBP device ...................................................................... mb/google/trulo: Enable EC MKBP device MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:357521411 TEST=Build coreboot and switch tablet mode on orisa. Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83819 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h index 145035a..3d2fc5a 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/ec.h @@ -68,6 +68,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic712f53fb4063347c38df05167f0100afc06f979 Gerrit-Change-Number: 83819 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
by Saurabh Mishra (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Subrata Banik. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83635?usp=email to look at the new patch set (#71). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till romstage List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/chip.h A src/soc/intel/pantherlake/chipset.cb A src/soc/intel/pantherlake/include/soc/gpe.h A src/soc/intel/pantherlake/include/soc/meminit.h A src/soc/intel/pantherlake/include/soc/msr.h A src/soc/intel/pantherlake/include/soc/pmc.h A src/soc/intel/pantherlake/include/soc/romstage.h A src/soc/intel/pantherlake/include/soc/soc_chip.h A src/soc/intel/pantherlake/include/soc/systemagent.h A src/soc/intel/pantherlake/meminit.c A src/soc/intel/pantherlake/reset.c A src/soc/intel/pantherlake/romstage/Makefile.mk A src/soc/intel/pantherlake/romstage/fsp_params.c A src/soc/intel/pantherlake/romstage/romstage.c A src/soc/intel/pantherlake/romstage/systemagent.c 17 files changed, 1,133 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/71 -- To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Gerrit-Change-Number: 83635 Gerrit-PatchSet: 71 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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[S] Change in coreboot[main]: util/liveiso/nixos/graphical: Preconfigure some Gnome settings
by Felix Singer (Code Review) 09 Aug '24

09 Aug '24

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83853?usp=email ) Change subject: util/liveiso/nixos/graphical: Preconfigure some Gnome settings ...................................................................... util/liveiso/nixos/graphical: Preconfigure some Gnome settings These settings are not a must, but nice to have. The most noteworthy setting is `sleep-inactive-ac-type`, which is set to `nothing` so that the target doesn't go into suspend when AC is used as power supply and it's unused for a while. Change-Id: I9a6e3eb88427f94f504a6b991a98b1b51e11bc19 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/liveiso/nixos/graphical.nix 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/83853/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a6e3eb88427f94f504a6b991a98b1b51e11bc19 Gerrit-Change-Number: 83853 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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