Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Saurabh Mishra.
Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83635?usp=email
to look at the new patch set (#68).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,120 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/68
--
To view, visit https://review.coreboot.org/c/coreboot/+/83635?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Gerrit-Change-Number: 83635
Gerrit-PatchSet: 68
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Attention is currently required from: Cliff Huang, Saurabh Mishra.
Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 17:
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/b2f58497_3af5be2e?us… :
PS17, Line 336: config FSP_FD_PATH
> Adding it back, to keep the recipe buildable. Seeing build issue w/o this config in standalone env.
I don't understand why you've encountered a compilation issue. Ideally, this configuration depends on FSP_USE_REPO, and I don't see that PTL SoC ever selects that configuration. Therefore, FSP_FD_PATH is just a stale path. Please avoid adding code before its time. It only makes sense to add this Kconfig after Intel releases the FSP.fd in external GitHub. If you want to use a standalone build, be sure to override it from the .config file, not from the PTL Kconfig.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Gerrit-Change-Number: 83798
Gerrit-PatchSet: 17
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Comment-Date: Fri, 09 Aug 2024 11:55:06 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com>
Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83851?usp=email )
Change subject: util/liveiso/nixos/graphical: Replace PulseAudio with PipeWire
......................................................................
util/liveiso/nixos/graphical: Replace PulseAudio with PipeWire
PipeWire is the successor of PulseAudio. So use that instead.
Change-Id: Ib557925e481ab72a31a64c4bf353a261dff4296d
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M util/liveiso/nixos/graphical.nix
1 file changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/83851/2
--
To view, visit https://review.coreboot.org/c/coreboot/+/83851?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib557925e481ab72a31a64c4bf353a261dff4296d
Gerrit-Change-Number: 83851
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Attention is currently required from: Cliff Huang, Subrata Banik.
Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83798?usp=email
to look at the new patch set (#17).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/me.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
M src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/me.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
39 files changed, 3,685 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/17
--
To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Gerrit-Change-Number: 83798
Gerrit-PatchSet: 17
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>