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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 65:
(10 comments)
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/52d38cca_5105b7f1?us… :
PS64, Line 6: 9
is this a 9W silicon ?
what is the source behind this configuration ?
https://review.coreboot.org/c/coreboot/+/83635/comment/5a575b1f_7626f28b?us… :
PS64, Line 13: 100
why 100 ?
https://review.coreboot.org/c/coreboot/+/83635/comment/f9211982_454770f8?us… :
PS64, Line 17: off
`on` may be ?
https://review.coreboot.org/c/coreboot/+/83635/comment/805756cb_6155d261?us… :
PS64, Line 48: device pci 08.0 alias gna off end
i don't see this device listed inside PTL EDS 815002
https://review.coreboot.org/c/coreboot/+/83635/comment/d7361308_cd4fe07b?us… :
PS64, Line 49: off
want to keep crashlog `on` ?
https://review.coreboot.org/c/coreboot/+/83635/comment/5fd5aef8_35c5dcf7?us… :
PS64, Line 65: end
Please add
```
chip drivers/usb/acpi
device usb 3.3 alias tcss_usb3_port3 off end
end
```
File src/soc/intel/pantherlake/p2sb.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/514c9b04_a879c8eb?us… :
PS64, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
please add this file as part of the ramstage CL as there is no consumer of p2sb.c in romstage
File src/soc/intel/pantherlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/ac4dcbd3_b8e96902?us… :
PS64, Line 36: timestamp_add_now(TS_CSE_FW_SYNC_START);
we have added these timestamp inside `cse_fw_sync` hence, please drop
```
void cse_fw_sync(void)
{
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
return;
timestamp_add_now(TS_CSE_FW_SYNC_START);
do_cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
```
https://review.coreboot.org/c/coreboot/+/83635/comment/29382d7c_401c12cc?us… :
PS64, Line 37: cse_fw_sync();
why are you enforcing CSE sync in romstage ?
Please follow romstage.c from MTL
```
if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
cse_fill_bp_info();
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
cse_fw_sync();
}
```
https://review.coreboot.org/c/coreboot/+/83635/comment/05cbb879_6034d7f0?us… :
PS64, Line 40:
missing
```
/* Update coreboot timestamp table with CSE timestamps */
if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
cse_get_telemetry_data();
```
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Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83845?usp=email )
Change subject: mb/google/brya/var/nova: Remove TCSS XHCI setting
......................................................................
mb/google/brya/var/nova: Remove TCSS XHCI setting
This patch removes the TCSS XHCI and TCSS DMA related setting from the
devicetree to solve the genesys hub enumeration issue.
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
---
M src/mainboard/google/brya/variants/nova/overridetree.cb
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/83845/1
diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb
index 35cf84b..4179093 100644
--- a/src/mainboard/google/brya/variants/nova/overridetree.cb
+++ b/src/mainboard/google/brya/variants/nova/overridetree.cb
@@ -257,9 +257,6 @@
end
end
device ref pmc hidden end
- device ref tcss_xhci off end
- device ref tcss_dma0 off end
- device ref tcss_dma1 off end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
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Attention is currently required from: Cliff Huang, Jérémy Compostella, Ravishankar Sarawadi, Saurabh Mishra.
Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#65).
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
18 files changed, 1,156 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/65
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/65
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Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/76591?usp=email )
Change subject: [RFC] Add UPL FDT handoff
......................................................................
Patch Set 18:
(4 comments)
This change is ready for review.
File payloads/Kconfig:
https://review.coreboot.org/c/coreboot/+/76591/comment/687e677c_3b6bd9c8?us… :
PS17, Line 194: # payload none only implies that we don't build with a payload, but it can later be added via CBFS, which makes creating handoff still necessary.
: choice
> I think that this shouldn't use a choice - we may want one or both enabled.
You can't have both. Either you pass FDT as argument to the payload or coreboot tables.
File payloads/libpayload/arch/arm/coreboot.c:
https://review.coreboot.org/c/coreboot/+/76591/comment/aaf82c67_bfec1531?us… :
PS17, Line 60: if (CONFIG(LP_UPL))
> You could just have a look at the cb_header_ptr to see what kind of handoff it is at runtime.
Sure but you would always need to compile in both handoffs. Not sure if that is worth the tradeoff.
File src/drivers/uart/pl011.c:
https://review.coreboot.org/c/coreboot/+/76591/comment/3abe4986_3e8db76a?us… :
PS15, Line 84: //TODO test
> still a todo?
Done
File src/drivers/uart/uart8250io.c:
https://review.coreboot.org/c/coreboot/+/76591/comment/5be2592a_5f61255b?us… :
PS15, Line 138: #define FDT_IORESOURCE_FLAG 0x100000000
> it just jumped out at me as being unusual, if nobody else has a problem with it, then I'm good with […]
Acknowledged
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Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83310?usp=email )
Change subject: mb/intel/mtlrvp: Set USB2-10 as cnvi_wifi bluetooth companion device
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
we need to remove bt_companion from here as well.
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Change subject: soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
......................................................................
soc/intel/cmn/block/cse: Add support for explicit CSE_RW_VERSION
This change adds support for specifying the CSE_RW_VERSION directly in
Kconfig.
* If `CONFIG_SOC_INTEL_CSE_RW_VERSION` is defined, its value will be
used directly as the CSE_RW version.
* Otherwise, the version will be extracted from the CSE_RW binary file
as before.
Platform prior to Intel Meteor Lake still requires to override the CSE
RW version using CONFIG_SOC_INTEL_CSE_RW_VERSION config rather reading
the CSE RW version from CSE RW partition.
BUG=b:327842062
TEST=CSE RW update successful on Karis with this patch using below
recipe:
1. Overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION="18.0.5.2269"
2. Without overriding the CONFIG_SOC_INTEL_CSE_RW_VERSION=""
Platform prior to Intel Meteor Lake would be using #1 and platform
starting with Meteor Lake expected to use #2 recipe.
Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83831
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/soc/intel/common/block/cse/Makefile.mk
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
Dinesh Gehlot: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk
index d41d735..9196cf8 100644
--- a/src/soc/intel/common/block/cse/Makefile.mk
+++ b/src/soc/intel/common/block/cse/Makefile.mk
@@ -91,6 +91,7 @@
$(CSE_LITE_ME_RW)-compression := LZMA
endif
+ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"")
INPUT_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
TEMP_FILE := $(shell mktemp)
OFFSETS := 16 18 20 22 # Offsets for CSE version components
@@ -105,6 +106,10 @@
rm -f $(TEMP_FILE)
$(eval CSE_RW_CBFS_VERSION := $(shell printf "%d.%d.%d.%d" $(CSE_VERSION_MAJOR)$(CSE_VERSION_MINOR)$(CSE_VERSION_HOTFIX)$(CSE_VERSION_BUILD)))
@echo '$(CSE_RW_CBFS_VERSION)' > $@
+else
+$(obj)/cse_rw.version:
+ @echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@
+endif
CSE_RW_VERSION = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME))
regions-for-file-$(CSE_RW_VERSION) = FW_MAIN_A,FW_MAIN_B
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I1327c813b7aef77c65766eb9c40003bb8a71d4b6
Gerrit-Change-Number: 83831
Gerrit-PatchSet: 3
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83828?usp=email )
Change subject: mb/google/fatcat: Add support for soldered-down memory
......................................................................
mb/google/fatcat: Add support for soldered-down memory
This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.
* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
* `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
* `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.
BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.
Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Reviewed-by: Pranava Y N <pranavayn(a)google.com>
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/Makefile.mk
A src/mainboard/google/fatcat/spd/Makefile.mk
3 files changed, 14 insertions(+), 0 deletions(-)
Approvals:
Pranava Y N: Looks good to me, approved
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Ravishankar Sarawadi: Looks good to me, approved
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 2c6ddd2..42a839c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -26,6 +26,7 @@
select BOARD_GOOGLE_FATCAT_COMMON
select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS
+ select MEMORY_SOLDERDOWN
select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_METEORLAKE_U_H
select SYSTEM_TYPE_LAPTOP
@@ -85,6 +86,11 @@
config MAINBOARD_PART_NUMBER
default "Fatcat" if BOARD_GOOGLE_FATCAT
+config MEMORY_SOLDERDOWN
+ def_bool n
+ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+ select HAVE_SPD_IN_CBFS
+
# FIXME: update as per board schematics
config TPM_TIS_ACPI_INTERRUPT
int
diff --git a/src/mainboard/google/fatcat/Makefile.mk b/src/mainboard/google/fatcat/Makefile.mk
index 11098e2..8c60c59 100644
--- a/src/mainboard/google/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/Makefile.mk
@@ -17,6 +17,8 @@
subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
diff --git a/src/mainboard/google/fatcat/spd/Makefile.mk b/src/mainboard/google/fatcat/spd/Makefile.mk
new file mode 100644
index 0000000..be4d98b
--- /dev/null
+++ b/src/mainboard/google/fatcat/spd/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Gerrit-Change-Number: 83828
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>