Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82975?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/xeon_sp/gnr: Remove VPD from GNR Kconfig
......................................................................
soc/intel/xeon_sp/gnr: Remove VPD from GNR Kconfig
Remove the unused config VPD from GNR Kconfig.
Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82975
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
Martin L Roth: Looks good to me, approved
Shuo Liu: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index abbf178..790f20e 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -15,7 +15,6 @@
select PLATFORM_USES_FSP2_X86_32
select HAVE_IOAT_DOMAINS
select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
- select VPD
help
Intel Granite Rapids support
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Gerrit-Change-Id: I3fc45ba05df5fc23e326081d6ce9e53b2046464c
Gerrit-Change-Number: 82975
Gerrit-PatchSet: 3
Gerrit-Owner: Chen, Gang C <gang.c.chen(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83829?usp=email )
Change subject: mb/google/nissa/var/teliks: Add DP AUX BIAS connect
......................................................................
mb/google/nissa/var/teliks: Add DP AUX BIAS connect
Because one side is not displayed when using type-c projection, the
configuration of DP AUX BIAS to SOC direct connection is added.
BUG=b:352263941
TEST=DP function of MB and DB workable
Change-Id: Id89d02212cdad549d1c26ed51a8d5af0f4e757c6
Signed-off-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83829
Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/teliks/overridetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Weimin Wu: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb
index 093a353..6ca555a 100644
--- a/src/mainboard/google/brya/variants/teliks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb
@@ -60,6 +60,26 @@
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
+ # SOC Aux orientation override:
+ # This is a bitfield that corresponds to up to 4 TCSS ports.
+ # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+ # TcssAuxOri = 0100b
+ # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
+ # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
+ # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+ # motherboard to USBC connector
+ register "tcss_aux_ori" = "5"
+
+ register "typec_aux_bias_pads[0]" = "{
+ .pad_auxp_dc = GPP_A19,
+ .pad_auxn_dc = GPP_A20
+ }"
+
+ register "typec_aux_bias_pads[1]" = "{
+ .pad_auxp_dc = GPP_E22,
+ .pad_auxn_dc = GPP_E23
+ }"
+
# FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{
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Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83317?usp=email )
(
10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
......................................................................
soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
This patch add a new Kconfig HAVE_SPECIFIC_GPMR and use it to include
soc/gpmr.h if necessary.
Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83317
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/gpmr/Kconfig
M src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h
2 files changed, 16 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Shuo Liu: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpmr/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig
index 06ababe..313b0cc 100644
--- a/src/soc/intel/common/block/gpmr/Kconfig
+++ b/src/soc/intel/common/block/gpmr/Kconfig
@@ -5,3 +5,13 @@
select SOC_INTEL_COMMON_BLOCK_PCR
help
Intel Processor common GPMR support
+
+if SOC_INTEL_COMMON_BLOCK_GPMR
+
+config USE_SOC_GPMR_DEFS
+ bool
+ default n
+ help
+ Specify if the SoC have specific GPMR register definitions.
+
+endif
diff --git a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h
index fb138f9..98ee837 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h
@@ -3,6 +3,10 @@
#ifndef SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H
#define SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H
+#if CONFIG(USE_SOC_GPMR_DEFS)
+#include <soc/pcr_gpmr.h>
+#else
+
#define GPMR_LPCLGIR1 0x2730
#define GPMR_DMICTL 0x2234
#define GPMR_DMICTL_SRLOCK (1 << 31)
@@ -24,4 +28,6 @@
#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8)
#define GPMR_EN BIT(31)
+#endif
+
#endif /* SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H */
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Attention is currently required from: Maximilian Brune, Philipp Hug.
Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83284?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: arch/riscv: Allow adding OpenSBI as external blob
......................................................................
Patch Set 2:
(1 comment)
File src/arch/riscv/Kconfig:
https://review.coreboot.org/c/coreboot/+/83284/comment/45a11c34_3799e8ad?us… :
PS2, Line 61: string
shouldn't this be a bool option?
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