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Change subject: arch/riscv: Allow adding OpenSBI as external blob
......................................................................
Patch Set 3:
(1 comment)
File src/arch/riscv/Kconfig:
https://review.coreboot.org/c/coreboot/+/83284/comment/e43669e0_472d7cb7?us… :
PS2, Line 61: string
> shouldn't this be a bool option?
ups
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Hello Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+2 by ron minnich, Verified+1 by build bot (Jenkins)
Change subject: arch/riscv: Allow adding OpenSBI as external blob
......................................................................
arch/riscv: Allow adding OpenSBI as external blob
The reasoning is that even though vendors currently tend to open source
their OpenSBI implementation, they often do so in their own repository.
So instead of adding all possible source repositories as submodules, we
shall allow specifying a path to an already compiled OpenSBI ELF file.
This is similar of what we currently do on ARM64 with the BL31 binary.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I6592ad90a254ca4ac9a6cee89404ad49274f0dea
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.mk
2 files changed, 24 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83284/3
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Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83872?usp=email )
Change subject: util/lint/lint-final-newlines: Supply dirs in row
......................................................................
util/lint/lint-final-newlines: Supply dirs in row
This just orders the EXCLUDED_DIRS directories in a row based manner,
since there are quite a few them now and it is arguably easier to read
and to add new directories if they are written in a row based fashion.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I802aece355bba4900e71824d802c4b2438726e84
---
M util/lint/lint-extended-015-final-newlines
1 file changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83872/1
diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines
index 4ea4536..18ca75b 100755
--- a/util/lint/lint-extended-015-final-newlines
+++ b/util/lint/lint-extended-015-final-newlines
@@ -14,7 +14,17 @@
PIDS=""
INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc'
-EXCLUDED_DIRS='src/vendorcode/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/\|^util/goswid/vendor'
+EXCLUDED_DIRS="\
+src/vendorcode/\|\
+cbfstool/lzma/\|\
+cbfstool/lz4/\|\
+Documentation/\|\
+build/\|\
+3rdparty/\|\
+\.git/\|\
+coreboot-builds/\|\
+util/nvidia/cbootimage/\|\
+^util/goswid/vendor"
EXCLUDED_FILES='\.gif$\|\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$\|\.apcb$'
HAVE_FILE=$(command -v file 1>/dev/null 2>&1; echo $?)
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Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich.
Hello Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: util/riscv: Add starfive Image building tool
......................................................................
util/riscv: Add starfive Image building tool
Add the tooling necessary to build an Image that can be found and
started by ROM code of the JH7110 SOC.
source: https://github.com/starfive-tech/Tools
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286
---
M util/lint/lint-extended-015-final-newlines
M util/lint/lint-stable-009-old-licenses
A util/riscv/starfive-jh7110-spl-tool/.gitignore
A util/riscv/starfive-jh7110-spl-tool/LICENSE
A util/riscv/starfive-jh7110-spl-tool/Makefile
A util/riscv/starfive-jh7110-spl-tool/README.md
A util/riscv/starfive-jh7110-spl-tool/crc32.c
A util/riscv/starfive-jh7110-spl-tool/spl_tool.c
8 files changed, 727 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83849/2
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Ravishankar Sarawadi has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 29:
(9 comments)
File src/soc/intel/pantherlake/acpi/serialio.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/e5725e5b_cf4e2a70?us… :
PS23, Line 47: Device (I3C0)
: {
: Name (_ADR, 0x00110000)
: Name (_DDN, "Serial IO I3C Controller 0")
: }
:
: Device (I3C1)
: {
: Name (_ADR, 0x00110002)
: Name (_DDN, "Serial IO I3C Controller 1")
: }
> do we have any usage for I3C debugging ? I don't believe so
Removing for now, would add if use case arises in future.
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/cfebd350_3bcf490d?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> based on my understanding, PTL-U only has UFS controller hence, not sure if keeping ufs. […]
UFS, IMO, we can add as feature enable later, removing for now.
File src/soc/intel/pantherlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/97b30acb_5952653e?us… :
PS23, Line 512: If (\_SB.PCI0.TDM1.IF30 != 1) {
: Return
: }
:
> as i have doubted previously as well, you are pushing some stale code w/o bothering looking into wha […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83772/comment/c5c77406_d9025292?us… :
PS23, Line 727: If (TRE0 == 1) {
> again same stale code […]
Fixed.
File src/soc/intel/pantherlake/acpi/tcss_dma.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/11089234_f6213341?us… :
PS23, Line 15: IF30, 1, /* ITBT FW Version Bit30 */
> don't need
Acknowledged
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/ddff7f8b_1db429ee?us… :
PS23, Line 12: Offset(0x51),
> why ? as there is no bit-field
Acknowledged
https://review.coreboot.org/c/coreboot/+/83772/comment/e11a25a9_db7b4b79?us… :
PS23, Line 56: 0xBAC
> use macro?
I could, I will try adding macros to a few more in next patch.
File src/soc/intel/pantherlake/acpi/tcss_xhci.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/791343cc_dc19e6b5?us… :
PS23, Line 166: 2
> 0 aka \_SB.PCI0.TDM1. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83772/comment/331fb9cc_6aae04b2?us… :
PS23, Line 183: 3
> 1 aka \_SB.PCI0.TDM1. […]
Acknowledged
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Alicja Michalska has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/80318?usp=email )
Change subject: util/superiotool/ite: Add extra dumps for IT8613E EC
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80318/comment/e2e32333_586cb8d3?us… :
PS6, Line 7: util/superiotool/ite: Add extra dumps for IT8613E EC
> Where did you get the register information from? Datasheet? Would be nice to specify in the commit m […]
I believe they have access to the datasheet under NDA with the vendor.
We discussed this patch during FOSDEM, when I mentioned my WIP port and issues I stumbled upon (with reading proper CPU temp value) but of course didn't see any contents of it as it was confidential.
I can test it next week to see if there's any improvement compared to previous patchset (as temperature reporting is the last issue preventing me from having my port being merged in upstream, it's been stable for a while now).
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
......................................................................
soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:
Found overlapped clkreq assignment on clk req 0
Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file
Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83865/2
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Felix Singer has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/83279?usp=email )
Change subject: RFC: util/autoport: Utilize text/template module
......................................................................
Patch Set 3:
(1 comment)
File util/autoport/templates/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/83279/comment/b5a79c5e_86073ed0?us… :
PS3, Line 9: len .PinConfig
> This is incorrect, as the original code used the length of PinConfig + 1 to account for the AZALIA_S […]
Can it be increased by 1 before passing it over?
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