coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
3913 discussions

[S] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Use boolean type where applicable
by Felix Singer (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Marvin Evers, Michael Strosche, Subrata Banik, Tarun, Tarun Tuli. Felix Singer has posted comments on this change by Michael Strosche. ( https://review.coreboot.org/c/coreboot/+/77374?usp=email ) Change subject: soc/intel/meteorlake/chip.h: Use boolean type where applicable ...................................................................... Patch Set 9: (6 comments) File src/soc/intel/meteorlake/chip.h: https://review.coreboot.org/c/coreboot/+/77374/comment/47d20793_1e729792?us… : PS8, Line 212: 1:Enable, 0:Disable > update the comment Done https://review.coreboot.org/c/coreboot/+/77374/comment/cd3eda68_0ef83dbc?us… : PS8, Line 235: * Default 0. Setting this to 1 disables > update Done https://review.coreboot.org/c/coreboot/+/77374/comment/533a9263_542d3a52?us… : PS8, Line 301: 1b:Enabled, 0b:Disabled > update Done https://review.coreboot.org/c/coreboot/+/77374/comment/6d86a64c_b791207a?us… : PS8, Line 451: Default 0. Setting this to 1 disables th > update Done https://review.coreboot.org/c/coreboot/+/77374/comment/cc7eb879_83ac0ab4?us… : PS8, Line 456: Enable(1)/Disable(0) > update Done https://review.coreboot.org/c/coreboot/+/77374/comment/55e8a9f3_b40a3aca?us… : PS8, Line 457: Default 0. Setting this to 1 > update Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Gerrit-Change-Number: 77374 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 12 Aug 2024 02:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: soc/intel/meteorlake/chip.h: Use boolean type where applicable
by Felix Singer (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Eric Lai, Felix Singer, Jakub Czapiga, Kapil Porwal, Marvin Evers, Michael Strosche, Subrata Banik, Tarun, Tarun Tuli. Felix Singer has uploaded a new patch set (#10) to the change originally created by Michael Strosche. ( https://review.coreboot.org/c/coreboot/+/77374?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Elyes Haouas, Code-Review+1 by Eric Lai, Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake/chip.h: Use boolean type where applicable ...................................................................... soc/intel/meteorlake/chip.h: Use boolean type where applicable Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Signed-off-by: Michael Strosche <michael.strosche(a)gmail.com> --- M src/soc/intel/meteorlake/chip.h 1 file changed, 37 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/77374/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77374?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd Gerrit-Change-Number: 77374 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michael Strosche <michael.strosche(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[M] Change in coreboot[main]: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config
by Morris Hsu (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: David Wu, Karthik Ramasubramanian, Ren Kuo, Shelley Chen. Hello David Wu, Karthik Ramasubramanian, Ren Kuo, Shelley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83874?usp=email to look at the new patch set (#5). Change subject: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config ...................................................................... mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config 1.Set unused device's GPIOs to NC based on fw_config. 2.Disable config for nvme, ufs and CNVi based on fw_config. 3.Add fw_config STORAGE_UNKNOWN to enable all storages for the first boot in factory. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge check fw_config messages in ap log verify devices on/off by fw_config on jubilant Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk A src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/variant.c 4 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83874/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/83874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Gerrit-Change-Number: 83874 Gerrit-PatchSet: 5 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config
by Morris Hsu (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: David Wu, Karthik Ramasubramanian, Ren Kuo, Shelley Chen. Morris Hsu has posted comments on this change by Morris Hsu. ( https://review.coreboot.org/c/coreboot/+/83874?usp=email ) Change subject: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Gerrit-Change-Number: 83874 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Aug 2024 02:08:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config
by Morris Hsu (Code Review) 12 Aug '24

12 Aug '24

Morris Hsu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83874?usp=email ) Change subject: mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config ...................................................................... mb/google/brox/jubilant: Disabe devcies and GPIOs by fw_config 1.Set unused device's GPIOs to NC based on fw_config. 2.Diable config for nvme, ufs and CNVi based on fw_config. 3.Add fw_config STORAGE_UNKNOWN to enable all storages for the first boot in factory. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge check fw_config messages in ap log verify devices on/off by fw_config on jubilant Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk A src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/variant.c 4 files changed, 120 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83874/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Gerrit-Change-Number: 83874 Gerrit-PatchSet: 2 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: Morris.
by Morris Hsu (Code Review) 12 Aug '24

12 Aug '24

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83874?usp=email ) Change subject: Morris. ...................................................................... Morris. Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk A src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/variant.c 4 files changed, 120 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83874/1 diff --git a/src/mainboard/google/brox/variants/jubilant/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/Makefile.mk index 3ed385f..878643e 100644 --- a/src/mainboard/google/brox/variants/jubilant/Makefile.mk +++ b/src/mainboard/google/brox/variants/jubilant/Makefile.mk @@ -5,6 +5,7 @@ romstage-y += gpio.c romstage-y += memory.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/jubilant/fw_config.c b/src/mainboard/google/brox/variants/jubilant/fw_config.c new file mode 100644 index 0000000..14b83a8 --- /dev/null +++ b/src/mainboard/google/brox/variants/jubilant/fw_config.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config fp_disable_pads[] = { + /* D2 : ISH_GP2 ==> EN_FP_PWR (NC) */ + PAD_NC(GPP_D2, NONE), + /* GPP_D3 : IPCH_FP_BOOT0 (active high) (NC) */ + PAD_NC(GPP_D3, NONE), + /* GPP_D15 : FPMCU_RST_J_SUB_L (active low) (NC) */ + PAD_NC(GPP_D15, NONE), + /* GPP_F15 : FP GSPI INT (NC) */ + PAD_NC(GPP_F15, NONE), + /* GPP_F11 : FP GSPI CLK (NC) */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 : FP GSPI DO (NC) */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 : FP GSPI DI (NC) */ + PAD_NC(GPP_F13, NONE), + /* GPP_F16 : FP GSPI CS (NC) */ + PAD_NC(GPP_F16, NONE), +}; + +static const struct pad_config lte_disable_pads[] = { + /* GPP_E11 : WWAN_CFG0 */ + PAD_NC(GPP_E11, NONE), + /* GPP_E17 : WWAN_CFG02 */ + PAD_NC(GPP_E17, NONE), + /* GPP_D7 :WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_D7, NONE), + /* GPP_D5 : WWAN_SAR_ODL */ + PAD_NC(GPP_D5, NONE), + /* GPP_F21 : WWAN_FCPO_L */ + PAD_NC(GPP_F21, NONE), + /* GPP_S4 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_S5, NONE), + /* GPP_F6 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_F6, NONE), + /*　GPP_A12 :　WWAN_PWR_EN　*/ + PAD_NC(GPP_A12, NONE), + /* GPP_H23 : WWAN_RST_L */ + PAD_NC(GPP_H23, NONE), +}; + +static const struct pad_config nvme_disable_pads[] = { + /* GPP_F9 : SSD_PERST_L */ + PAD_NC(GPP_F9, NONE), + /* GPP_D11 : EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_D8 : SSD_CLKREQ_ODL */ + PAD_NC(GPP_D8, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned. Exiting...\n"); + return; + } + + if (fw_config_probe(FW_CONFIG(FPMCU, FPMCU_ABSENT))) { + printk(BIOS_INFO, "Disable Fingerprint GPIOs by fw_config.\n"); + gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads)); + } + + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n"); + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n"); + gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); + } + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 4110f43..09970cc 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -41,9 +41,8 @@ device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Soc"" - register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Fan-Inlet"" ## Active Policy register "policies.active" = "{ @@ -102,7 +101,7 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 18000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, @@ -294,6 +293,7 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -331,9 +331,11 @@ device generic 0 alias ish_conf on end end probe STORAGE STORAGE_UFS + probe STORAGE STORAGE_UNKNOWN end device ref ufs on probe STORAGE STORAGE_UFS + probe STORAGE STORAGE_UNKNOWN end device ref i2c0 on chip drivers/i2c/generic @@ -354,15 +356,6 @@ register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end - chip drivers/i2c/hid - register "generic.hid" = ""PIXA2303"" - register "generic.desc" = ""PIXA Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)" - register "generic.wake" = "GPE0_DW2_03" - register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 0x68 on end - end end #I2C0 device ref i2c1 on chip drivers/i2c/hid diff --git a/src/mainboard/google/brox/variants/jubilant/variant.c b/src/mainboard/google/brox/variants/jubilant/variant.c index e085a86..6f8ee01 100644 --- a/src/mainboard/google/brox/variants/jubilant/variant.c +++ b/src/mainboard/google/brox/variants/jubilant/variant.c @@ -3,6 +3,7 @@ #include <assert.h> #include <baseboard/variants.h> #include <chip.h> +#include <device/device.h> #include <fw_config.h> #include <sar.h> @@ -11,6 +12,11 @@ if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI))) { printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; + config->cnvi_bt_audio_offload = true; + }else { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + config->cnvi_bt_audio_offload = false; } } @@ -18,3 +24,26 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } + +void variant_devtree_update(void) +{ + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + struct device *nvme_rp = DEV_PTR(pcie4_0); + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + printk(BIOS_INFO, "fw_config storage is unknown so enable all storage devices.\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + printk(BIOS_INFO, "NVMe disabled by fw_config.\n"); + nvme_rp->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config.\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/83874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181 Gerrit-Change-Number: 83874 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: arch/riscv: Remove ram probing
by Maximilian Brune (Code Review) 12 Aug '24

12 Aug '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83873?usp=email ) Change subject: arch/riscv: Remove ram probing ...................................................................... arch/riscv: Remove ram probing Previously RAM probing was neccessary for our QEMU-RISCV target in order to find the available amount of memory. Now we get the memory from the devicetree propagated by QEMU, so there is no reason to keep it anymore. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c --- M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/exception.h D src/arch/riscv/ramdetect.c M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/cbmem.c 7 files changed, 6 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83873/1 diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index 6754c22..c370e3e 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -96,7 +96,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.S -romstage-y += ramdetect.c # Build the romstage @@ -120,7 +119,6 @@ ramstage-y = ramstage-y += ramstage.S -ramstage-y += ramdetect.c ramstage-y += tables.c ramstage-y += payload.c ramstage-y += fit_payload.c diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 2eb575e..976d752 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -26,7 +26,7 @@ } void redirect_trap(void); -void default_trap_handler(struct trapframe *tf); +void trap_handler(struct trapframe *tf); void handle_supervisor_call(struct trapframe *tf); #endif diff --git a/src/arch/riscv/ramdetect.c b/src/arch/riscv/ramdetect.c deleted file mode 100644 index 048d396..0000000 --- a/src/arch/riscv/ramdetect.c +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <arch/exception.h> -#include <types.h> -#include <console/console.h> -#include <device/mmio.h> -#include <ramdetect.h> -#include <arch/smp/spinlock.h> -#include <vm.h> - -static enum { - ABORT_CHECKER_NOT_TRIGGERED, - ABORT_CHECKER_TRIGGERED, -} abort_state = ABORT_CHECKER_NOT_TRIGGERED; - -extern void (*trap_handler)(struct trapframe *tf); - -static int get_instruction_len(uintptr_t addr) -{ - uint16_t ins = read16p(addr); - - /* - * 16-bit or 32-bit instructions supported - */ - if ((ins & 0x3) != 3) { - return 2; - } else if ((ins & 0x1f) != 0x1f) { - return 4; - } - - die("Not a 16bit or 32bit instruction 0x%x\n", ins); -} - -static void ramcheck_trap_handler(struct trapframe *tf) -{ - abort_state = ABORT_CHECKER_TRIGGERED; - - /* - * skip read instruction. - */ - int insn_size = get_instruction_len(tf->epc); - - write_csr(mepc, read_csr(mepc) + insn_size); -} - -int probe_mb(const uintptr_t dram_start, const uintptr_t size) -{ - uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); - void *ptr = (void *)addr; - - abort_state = ABORT_CHECKER_NOT_TRIGGERED; - trap_handler = ramcheck_trap_handler; - barrier(); - read32(ptr); - trap_handler = default_trap_handler; - barrier(); - printk(BIOS_DEBUG, "%lx is %s DRAM\n", dram_start + size * MiB, - abort_state == ABORT_CHECKER_NOT_TRIGGERED ? "" : "not"); - - return abort_state == ABORT_CHECKER_NOT_TRIGGERED; -} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 2f22ce2..6a151a6 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -109,9 +109,7 @@ } } -void (*trap_handler)(struct trapframe *tf) = default_trap_handler; - -void default_trap_handler(struct trapframe *tf) +void trap_handler(struct trapframe *tf) { if (tf->cause & 0x8000000000000000ULL) { interrupt_handler(tf); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index d6a93b0..d81f884 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -120,8 +120,7 @@ mv a0,sp # put trapframe as first argument - LOAD t0, trap_handler - jalr t0 + jal trap_handler trap_return: restore_regs diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 27b1b58..9b5a6f0 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -69,13 +69,6 @@ int default 0 -config DRAM_SIZE_MB - int - default 16383 - help - Qemu maps MMIO at ALIGN_UP(top_of_mem, 16 * GiB) - To avoid confusing the dram probing algorithm, avoid large dram sizes (16G - 1m) - config OPENSBI_PLATFORM string default "generic" diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c index 3e11415..ff3f5db 100644 --- a/src/mainboard/emulation/qemu-riscv/cbmem.c +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> @@ -11,9 +12,7 @@ uint64_t top; top = fdt_get_memory_top((void *)HLS()->fdt); - if (top) - return MIN(top, (uint64_t)4 * GiB - 1); + ASSERT_MSG(top, "Failed reading memory range from FDT"); - size_t dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); - return (uintptr_t)_dram + dram_mb_detected * MiB; + return MIN(top, (uint64_t)4 * GiB - 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c Gerrit-Change-Number: 83873 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XL] Change in coreboot[main]: util/ifdtool: bsd-style prototypes, main() on top
by Maximilian Brune (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: Leah Rowe. Maximilian Brune has posted comments on this change by Leah Rowe. ( https://review.coreboot.org/c/coreboot/+/71024?usp=email ) Change subject: util/ifdtool: bsd-style prototypes, main() on top ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71024/comment/2fd30675_a1f290ff?us… : PS1, Line 17: Finally, split types and names (for each function) to a new line. For example: : : int : main(int argc, char *argv[]) : { : : } : : Instead of: : : int main(int argc, char *argv[]) : { : : } besides the fact that it doesn't fit in our coding style I also don't see any advantages to that. It is mostly just a pain for searching (aka grepping) of functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/71024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9fbf4463fe36ea8cabfaa873bdde73cd3de0024 Gerrit-Change-Number: 71024 Gerrit-PatchSet: 1 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Comment-Date: Sun, 11 Aug 2024 22:56:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: util/ifdtool/ifdtool.c: Add validation exception
by Maximilian Brune (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: Stefan Reinauer. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/79368?usp=email ) Change subject: util/ifdtool/ifdtool.c: Add validation exception ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d Gerrit-Change-Number: 79368 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Aug 2024 22:49:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: sb/intel/common: Validate IFD by default
by Maximilian Brune (Code Review) 12 Aug '24

12 Aug '24

Attention is currently required from: Arthur Heymans, Bill XIE. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/73470?usp=email ) Change subject: sb/intel/common: Validate IFD by default ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/73470?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia11f56a5bbe3259c3ebae810036d1aac00a911f7 Gerrit-Change-Number: 73470 Gerrit-PatchSet: 12 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 11 Aug 2024 22:49:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2024