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Change subject: vc/intel/fsp: Update ADL N FSP headers from v5021.00 to v5132.00
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
this update seems to not have a binary-compatible upd interface to the previous version, so i wonder if this has some side effects on other mainboards. i also wonder if these files are used at all, since the next commit selects both SOC_INTEL_ALDERLAKE_PCH_N and FSP_TYPE_IOT which should result in the fsp headers from the fsp repository being used and not the ones this patch updates
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83976?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: Docs: Fix broken header references
......................................................................
Docs: Fix broken header references
MyST Parser automatically generates label "slugs" for headers which
should be used to reference them from links [1]. These labels are in
"slug-case", i.e. the original header text in lower case separated by
dashes, with punctuation removed. This fixes a few "cross-reference
target not found" warnings.
[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-sl…
Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/mainboard/lenovo/Ivy_Bridge_series.md
M Documentation/northbridge/intel/sandybridge/nri_freq.md
M Documentation/releases/coreboot-4.13-relnotes.md
M Documentation/superio/nuvoton/npcd378.md
4 files changed, 4 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
index 73d38fe..a7893e7 100644
--- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
+++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md
@@ -82,7 +82,7 @@
space for the `bios` region. This is usually referred to as *cleaning the ME* or
*stripping the ME*.
After reducing the Intel ME firmware size you must modify the original IFD,
-[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
+[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write
each ROM using an [external programmer].
Have a look at [me_cleaner] for more information.
diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md
index 45cac8d..0732870 100644
--- a/Documentation/northbridge/intel/sandybridge/nri_freq.md
+++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md
@@ -160,7 +160,7 @@
slowest DIMMs' frequency will be selected, to prevent over-clocking it.
The selected frequency gives the PLL multiplier to operate at. In case the PLL
-locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
+locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for
all DIMMs. At this point it's not possible to change the multiplier again,
until the system has been powered off. In case the PLL doesn't lock, the next
smaller multiplier will be used until a working multiplier will be found.
diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md
index 600bf67..29374d1 100644
--- a/Documentation/releases/coreboot-4.13-relnotes.md
+++ b/Documentation/releases/coreboot-4.13-relnotes.md
@@ -214,7 +214,7 @@
In order to minimize the usage of PCI bus mastering, the options we introduced in
this release will be dropped in a future release again. For more details, please
-see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot).
+see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering).
### Resource allocator v3
diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md
index 1cc081b..6e5bf66 100644
--- a/Documentation/superio/nuvoton/npcd378.md
+++ b/Documentation/superio/nuvoton/npcd378.md
@@ -78,7 +78,7 @@
### LDN8
Custom HWM space. It exposes 256 byte of IO config space.
-See [HWM](#HWM) for more details.
+See [HWM](#hwm) for more details.
## HWM
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Change subject: mb/hp: Move compaq_elite_8300_usdt into snb_ivb_desktops variants
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
i'll assume that the devicetree override has been reviewed in detail and submit this patch
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Change subject: drivers/soundwire: Support Realtek ALC722 codec
......................................................................
Patch Set 11:
(1 comment)
File src/drivers/soundwire/alc711/alc711.c:
PS11:
> > while i'm all for avoiding duplicate code, i don't like this approach too much, since when adding […]
yes, that's the problem i see with this patch
usually selecting the kconfig option for a driver only makes sure that it gets added to the build, so that the linker can resolve the symbols of the devicetree entry. here the same chip driver entry in the devicetree will basically be a different driver depending on which mutually exclusive kconfig option is set
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Change subject: [RFC] region: Hide struct region members
......................................................................
Patch Set 8:
(1 comment)
File src/commonlib/include/commonlib/region.h:
https://review.coreboot.org/c/coreboot/+/79907/comment/8df1e8b3_b7dacda3?us… :
PS8, Line 80: #else
: #define _region_offset _region_internal_only__offset
: #define _region_size _region_internal_only__size
> I understand that in order for code that still accesses `offset` and `size` directly we need this `# […]
ok never mind. I got it now.
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Change subject: [RFC] region: Hide struct region members
......................................................................
Patch Set 8:
(2 comments)
File src/arch/arm/fit_payload.c:
https://review.coreboot.org/c/coreboot/+/79907/comment/f32dc12f_e9ac7451?us… :
PS8, Line 3: /* FIXME: should use the high-level region api */
> Hmmm, the comments were probably a bit premature. The code seems to […]
I don't think we have an actual maintainer for the FIT payload support. I have only tried to use a FIT payload once (~1 year ago) and at the time it didn't even work (I think). I wouldn't be surprised if it still doesn't work and no one noticed, since no one uses it. If it were up to me I would just remove the FIT payload entirely and just use SELF (maybe generate a SELF from a FIT in build time like we do with everything else). But that is something for another time/patch.
I would suggest we ignore the FIT stuff and just move on with this patch (aka marking this as resolved).
One thing though: Can't `region-test.c` just use the getter/setter functions instead of directly accessing the properties?
File src/commonlib/include/commonlib/region.h:
https://review.coreboot.org/c/coreboot/+/79907/comment/f6292274_b72a16cb?us… :
PS8, Line 80: #else
: #define _region_offset _region_internal_only__offset
: #define _region_size _region_internal_only__size
I understand that in order for code that still accesses `offset` and `size` directly we need this `#ifdef`.
But for what purposes does the content of `#else` exist? Why redefine it as something else even if `REGION_INTERNAL_STRUCTURES` is not set? I feel like I am missing something.
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