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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> > sure. let me introduce SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD in soc. […]
understood. I will bring this up and the chromebase case.
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 46:
(2 comments)
Patchset:
PS46:
> looks like you need to add macros like https://review.coreboot. […]
Subrata, I don't quite get it this time:( I don't see macros from the patchset you mentioned. Can you give me more info? Thx
File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/83789/comment/28cbb3e0_453b6cec?us… :
PS17, Line 544: #define GPP_VGPIO0 246
> > The response is that these are for internal only and there is no plan to provide VGPIO info in EDS […]
PTL EDS includes VGPIO_TS0...VGPIO_THC3 in community3. I know we will need the ones for THC for enabling wake. I don't know if we will use any other vGPIO PADs. Let's bring up those info needed for code review from EDS in Monday's meeting.
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> sure. let me introduce SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD in soc.
>
> Let's bring up EDS issue on our Monday sync-up meeting because this will happen over time. I also feel that most of time spent during the review is due to the document info. I understand that it is very difficult to review without sufficient info from the external doc. I don't think even the EDS owners can make the decision at this time, but feedback to them in this particular topic of having the need of support DP with no retimer.
As I said, we should be able to review the code as long as you are able to share some source of the truth in the form of register definitions. At this point there is nothing where I should look at and confirm what/how you are doing things are only correct. Therefore, a bare minimal req for me to review the code is to have the register definitions (which is missing at this moment)
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 11:
(9 comments)
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/8230210a_3255b518?us… :
PS11, Line 15: #define SET_PSYSPL2(e, w) ((e) * (w) / 100)
If not setting Psys please remove it.
https://review.coreboot.org/c/coreboot/+/83752/comment/9077036a_e1c32924?us… :
PS11, Line 16: SET_PL2
If not setting PL2, please remove it.
https://review.coreboot.org/c/coreboot/+/83752/comment/ddc91428_b5669365?us… :
PS11, Line 19: #define TENPOWERSIX 1000000
: #define TENPOWERTHREE 1000
:
Instead of TENPOWERSIX and TENPOWERTHREE, please define MILLIVOLT_TO_VOLT and MILLIAMP_TO_AMP. That way it is easy to understand.
https://review.coreboot.org/c/coreboot/+/83752/comment/df80936f_6007a926?us… :
PS11, Line 82: MILLIWATTS_TO_WATTS);
Indent it after the DIV_ROUND_UP open parenthesis.
https://review.coreboot.org/c/coreboot/+/83752/comment/360be0e4_0fe7ace0?us… :
PS11, Line 87: &volts_mv);
Same comment as above.
https://review.coreboot.org/c/coreboot/+/83752/comment/0a320876_21f1d8ff?us… :
PS11, Line 98: soc_config->tdp_pl4 = SET_PL4(40, watts);
Can you please add a table at the start of this function to provide an idea of what the PL4 will look like for different power adapter ratings?
https://review.coreboot.org/c/coreboot/+/83752/comment/557f7ed0_b4de5c8e?us… :
PS11, Line 102: watts);
Same comment as above.
https://review.coreboot.org/c/coreboot/+/83752/comment/3b20ffc7_13e370f0?us… :
PS11, Line 146: void variant_update_psys_power_limits
It seems not used anymore. If so, can we remove it. Also remove the function prototype in variants.h
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/23bfd33e_a085b684?us… :
PS9, Line 359: if (CONFIG(EC_GOOGLE_CHROMEEC) && (!google_chromeec_is_battery_present_and_above_critical_threshold())) {
> for example how crashlog or platform debug consent is enabled in line 356 / 370 […]
How about moving inside mainboard_memory_init_params override in brox mainboard. That way it is mainboard specific. Also it will address batteryless scenario in chromebox form factor in other alderlake platforms.
Finally is MaxBootFrequency related to Trace Feature. As a casual reviewer, it does not look like so. But you might know the details more.
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Change subject: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84019/comment/26f4c5c7_4b150247?us… :
PS1, Line 438: #
> give one space between `#` and start
Done
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84019?usp=email
to look at the new patch set (#3).
Change subject: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
......................................................................
mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Build and boot nivviks. Monitor the camera LED blinking
during boot.
Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d
Signed-off-by: Sowmya V <v.sowmya(a)intel.com>
---
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
1 file changed, 18 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84019/3
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Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> > Subrata, […]
sure. let me introduce SOC_INTEL_COMMON_TCSS_SKIP_AUX_PAD in soc.
Let's bring up EDS issue on our Monday sync-up meeting because this will happen over time. I also feel that most of time spent during the review is due to the document info. I understand that it is very difficult to review without sufficient info from the external doc. I don't think even the EDS owners can make the decision at this time, but feedback to them in this particular topic of having the need of support DP with no retimer.
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, V Sowmya.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84019?usp=email
to look at the new patch set (#2).
Change subject: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
......................................................................
mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Build and boot nivviks. Monitor the camera LED blinking
during boot.
Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d
Signed-off-by: Sowmya V <v.sowmya(a)intel.com>
---
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
1 file changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/84019/2
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Gerrit-Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d
Gerrit-Change-Number: 84019
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, V Sowmya.
Subrata Banik has posted comments on this change by V Sowmya. ( https://review.coreboot.org/c/coreboot/+/84019?usp=email )
Change subject: mb/google/nissa/var/nivviks: Prevent camera LED blinking during boot
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84019/comment/cb476a28_e9125c99?us… :
PS1, Line 438: #
give one space between `#` and start
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