coreboot-gerrit August 2024

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[XS] Change in coreboot[main]: [skolas]: Add reference to wifi_sar_0.hex file
by Poornima Tom (Code Review) 25 Aug '24

25 Aug '24

Hello Poornima Tom, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84060?usp=email to look at the new patch set (#4). Change subject: [skolas]: Add reference to wifi_sar_0.hex file ...................................................................... [skolas]: Add reference to wifi_sar_0.hex file Note: To test Change-Id: Ic3bb2088f970e829f43a49e0e3497049eccf2b6d Signed-off-by: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/skolas/variant.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/84060/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84060?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3bb2088f970e829f43a49e0e3497049eccf2b6d Gerrit-Change-Number: 84060 Gerrit-PatchSet: 4 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: drivers/spi: Stop using a variable-length array
by Nico Huber (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84059?usp=email ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... Patch Set 1: (3 comments) File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/84059/comment/96bec406_fe20f0f6?us… : PS1, Line 136: strain the stack strain *on* the stack https://review.coreboot.org/c/coreboot/+/84059/comment/acb74534_8c636447?us… : PS1, Line 137: static u8 buff[4 + MAX_FLASH_CMD_DATA_SIZE]; `+ ADDR_MOD` It's set to 1 for `CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE` (seems not used, but we should be prepared). https://review.coreboot.org/c/coreboot/+/84059/comment/8389b719_5e4dfb9c?us… : PS1, Line 317: chunk_len = MIN(MAX_FLASH_CMD_DATA_SIZE, chunk_len); > Not sure about this part, does it truncate the write properly? Should it be an assertion of some kin […] Seems fine to me. The caller of spi_flash_cmd_write_page_program(), and spi_crop_chunk() can already go below the page size. And I'm not aware of any SPI flash that would mind. -- To view, visit https://review.coreboot.org/c/coreboot/+/84059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I157ecec69c049ead06467b0328efd7d1a09bd268 Gerrit-Change-Number: 84059 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 25 Aug 2024 09:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: Makefile.mk: Add option to use '-Oz' over '-Os'
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Arthur Heymans has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77189?usp=email ) Change subject: Makefile.mk: Add option to use '-Oz' over '-Os' ...................................................................... Patch Set 8: (1 comment) File Makefile.mk: https://review.coreboot.org/c/coreboot/+/77189/comment/25c76e73_50d87366?us… : PS8, Line 629: CFLAGS_common += -Oz Not all versions of GCC support this. Add it via xcompile -- To view, visit https://review.coreboot.org/c/coreboot/+/77189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffdb8c7918d768ef3e8dba24e7fb6cadabfadd8e Gerrit-Change-Number: 77189 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 25 Aug 2024 09:47:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email ) Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64 ...................................................................... soc/intel/alderlake: Configure DDR5 Physical channel width to 64 A DDR5 DIMM internally has two channels each of width 32 bit. But the total physical channel width is 64 bit. This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5 Physical channel width to 64" Building with GCC LTO cought this bufferoverflow when assigning SPD addresses to a buffer. Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/meteorlake/meminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/84085/1 diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index 32ab358..dae175f 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -8,7 +8,7 @@ #define LPX_PHYSICAL_CH_WIDTH 16 #define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH) -#define DDR5_PHYSICAL_CH_WIDTH 32 +#define DDR5_PHYSICAL_CH_WIDTH 64 /* 32*2 */ #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH) static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) -- To view, visit https://review.coreboot.org/c/coreboot/+/84085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545 Gerrit-Change-Number: 84085 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84033?usp=email to look at the new patch set (#17). Change subject: [NOT_FOR_MERGE]Kconfig: Build all targets with LTO ...................................................................... [NOT_FOR_MERGE]Kconfig: Build all targets with LTO ARM with GCC LTO fails hard. Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84033/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/84033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3be6a71fdf9c2d1e14226550daa734b7cdc7e350 Gerrit-Change-Number: 84033 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: car.ld: Fix bug with LLD
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84052?usp=email ) Change subject: car.ld: Fix bug with LLD ...................................................................... Abandoned It looks like symbols inside sections are actually relative which caused problems -- To view, visit https://review.coreboot.org/c/coreboot/+/84052?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cdd1b509bb9ff449e692109a4b674f8bfd732a4 Gerrit-Change-Number: 84052 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/cavium: Fix non matching types
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84084?usp=email ) Change subject: soc/cavium: Fix non matching types ...................................................................... soc/cavium: Fix non matching types There is no struct device *dev equivalent of this function. Clang LTO warns about mismatching types. Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/common/include/soc/ecam.h 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/84084/1 diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c index ff3e709..db5090f 100644 --- a/src/soc/cavium/cn81xx/ecam0.c +++ b/src/soc/cavium/cn81xx/ecam0.c @@ -181,7 +181,7 @@ dev_path(dev)); return -1; } - bar = ecam0_get_bar_val(dev, bar_idx); + bar = ecam0_get_bar_val(pcidev_bdf(dev), bar_idx); if (!bar) { printk(BIOS_ERR, "%s: Failed to find MSI-X bar\n", dev_path(dev)); diff --git a/src/soc/cavium/common/include/soc/ecam.h b/src/soc/cavium/common/include/soc/ecam.h index b0f10dc..534c165 100644 --- a/src/soc/cavium/common/include/soc/ecam.h +++ b/src/soc/cavium/common/include/soc/ecam.h @@ -3,14 +3,8 @@ #ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H #define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM_H -#ifdef __SIMPLE_DEVICE__ #include <device/pci_type.h> uint64_t ecam0_get_bar_val(pci_devfn_t dev, u8 bar); -#else -#include <device/device.h> - -uint64_t ecam0_get_bar_val(struct device *dev, u8 bar); -#endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22c8c9b9f350c53469a5d386db211969c8a41cf0 Gerrit-Change-Number: 84084 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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[XS] Change in coreboot[main]: arch/x86/car.ld: Fix overlapping regions
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Angel Pons, Arthur Heymans, Jérémy Compostella. Hello Angel Pons, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84048?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons Change subject: arch/x86/car.ld: Fix overlapping regions ...................................................................... arch/x86/car.ld: Fix overlapping regions The fspm_rc_heap is already accounted for inside .car.data. Some linkers like LLD do not like overlapping regions so remove this. Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/84048/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I058bd6790afc313e06f1888e5b783d97b7e93b1e Gerrit-Change-Number: 84048 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: [WIP]arch/x86: Make bootblock.ld LLD compatible
by Arthur Heymans (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84045?usp=email to look at the new patch set (#14). Change subject: [WIP]arch/x86: Make bootblock.ld LLD compatible ...................................................................... [WIP]arch/x86: Make bootblock.ld LLD compatible Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/bootblock.ld M src/cpu/x86/reset16.S 2 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/84045/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Gerrit-Change-Number: 84045 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: Docs/conf.py: Explicitly define external URL schemes
by Nico Huber (Code Review) 25 Aug '24

25 Aug '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/84069?usp=email ) Change subject: Docs/conf.py: Explicitly define external URL schemes ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Rebase hopefully triggers Jenkins... -- To view, visit https://review.coreboot.org/c/coreboot/+/84069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e1c76b2bacbacaa06340f940c76b50de38e43e8 Gerrit-Change-Number: 84069 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 25 Aug 2024 09:21:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit August 2024