Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83280?usp=email )
Change subject: mb/lenovo/t420: Use vendor default power limits
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83280/comment/6d82d9e3_d7464071?us… :
PS6, Line 10:
> How can users test the effects?
Set TCC offset to 15 degrees Celcius in devicetree, compile and flash, run a stress test such as `$ stress-ng -c 8 --cpu-method matrixprod`. CPU temperature should not exceed Tjmax - TCCoffset, in the case of 3940XM with TCC offset = 15 CPU temperature stays at or below 90 degrees Celcius.
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Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email )
Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
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Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83271/comment/166666fb_951365d9?us… :
PS8, Line 8:
> Can you elaborate?
Test 1: Set 1-core turbo ratio limit to 41x in devicetree. Compile and flash. `$ rdmsr 0x1ad` returns 0x0000000025252629 => turbo ratio limits are 37x/37x/38x/41x.
Test 2: Set 3-core turbo ratio limit to 41x in devicetree. Compile and flash. `$ rdmsr 0x1ad` returns 0x0000000025292627 => turbo ratio limits are 37x/41x/38x/39x.
Test 3: Set all turbo ratio limits to 41x in devicetree. Compile and flash. `$ rdmsr 0x1ad` returns 0x0000000029292929 => turbo ratio limits are 41x/41x/41x/41x
Also used Intel PCM to confirm single-core clock reaches 4.1 GHz under load.
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Arthur Heymans has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83594?usp=email )
Change subject: arch/x86/Kconfig: Stop building ARM verstage with clang
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83594/comment/ed88ca2c_8f754cc3?us… :
PS1, Line 9: We have never intended to build ARM verstage with clang (see CB:69701).
> That was my intention though. Why is building ARM verstage with clang a problem?
Ok so let me rephrase. It was my intention to enable clang for the ARM verstage and that worked on some point. I was not aware of CB:69701, which gives no detailed reason for removing clang support. I just tested guybrush with clang build verstage and it builds fine. So I'm wondering what the problem is.
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Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
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Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83540/comment/eaaf771b_7b500a1e?us… :
PS5, Line 7: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements
> Do you mean the summary/title? […]
Agree, changing to `mtl` made the tittle short enough
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Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
......................................................................
soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
TEST=None
Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83540/7
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Change subject: soc/intel/mtl: Adjust CAR STACK_SIZE for coreboot compatibility This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to 512KB + 32KB, addressing a requirement specified by coreboot where stack usage is higher than 1KB alone.
......................................................................
soc/intel/mtl: Adjust CAR STACK_SIZE for coreboot compatibility
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
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Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83540/6
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