Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83548?usp=email )
Change subject: mb/google/brya/var/trulo: Add TCSS port descriptions
......................................................................
mb/google/brya/var/trulo: Add TCSS port descriptions
This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.
Additionally, implement the TCSS PMC MUX programming.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 32 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 56d96ff..03f7f9e 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -17,8 +17,28 @@
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB)
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+ # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+ # Bit 2 - C1 has a redriver which does SBU muxing.
+ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+ register "tcss_aux_ori" = "0"
+
device domain 0 on
device ref igpu on end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ end
+ end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
@@ -84,8 +104,20 @@
device ref ufs on end
device ref pch_espi on
chip ec/google/chromeec
+ use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port5 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ end
+ end
+ end
end
end
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
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Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81920?usp=email )
Change subject: drivers/soundwire: Support Realtek ALC722 codec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
I was comparing ALC 711 and ALC 722 (your CL) and felt that only change between those two drivers are .version, .part_id and .class.
Additionally, you can refactor the existing ALC 711 code to accommodate both codec (this will save the coding and review effort as well)
1.
```
static struct soundwire_address alc711_address = {
#if CONFIG(DRIVERS_SOUNDWIRE_ALC722)
.version = SOUNDWIRE_VERSION_1_2,
.class = MIPI_CLASS_SDCA
.part_id = MIPI_DEV_ID_REALTEK_ALC722,
#elif CONFIG(DRIVERS_SOUNDWIRE_ALC711)
.version = SOUNDWIRE_VERSION_1_1,
.class = MIPI_CLASS_NONE
.part_id = MIPI_DEV_ID_REALTEK_ALC711,
#else
#error "Select correct codec driver"
#endif
.manufacturer_id = MIPI_MFG_ID_REALTEK,
};
```
2.
```
config DRIVERS_SOUNDWIRE_ALC_BASE_7XX
bool
help
Base code for Realtek ALC7xxx Codec Soundwire Driver.
config DRIVERS_SOUNDWIRE_ALC711
bool
select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
Soundwire Driver for Realtek ALC711 device
config DRIVERS_SOUNDWIRE_ALC722
bool
select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
help
Soundwire Driver for Realtek ALC722 device
```
3.
```
ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC_BASE_7XX) += alc711.c
```
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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83565?usp=email )
Change subject: mb/google/brya/var/trulo: Add Thermal descriptions
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/trulo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83565/comment/d997772b_a54fb984?us… :
PS1, Line 198: register "policies.active" = "{
> > > We need different setting values to control Fan speed for 6W and 15W design, if 6W system has Fan.
> >
> >
> > Note: this is base CL for N/DOrisa to operational and we can always optimise these numbers once we have board in hand.
> >
> > >
> > > Is 6W design Fan based the system?
> >
> > Yes, we have fan in all the SKUs
>
> marking resolved as I hope we have an alignment here
thanks Sumeet, hopefully the Trulo reaches Intel office, you can update the thermal settings
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