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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83321/comment/697a5771_2067f40f?us… :
PS3, Line 7: src/
> Remove "src"
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/83321/comment/1594f402_a62e34b9?us… :
PS9, Line 8:
For a over 5000 diffstat, please elaborate on the chip and implementation.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: transcoder: Don't try to disable disabled DDI func
......................................................................
Patch Set 2:
(1 comment)
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https://review.coreboot.org/c/libgfxinit/+/83598/comment/04ca011d_75c31f62?… :
PS2, Line 18:
What device do you test with?
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Change subject: mb/google/nissa/var/riven: Add Fn key scancode
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Patch Set 1: Code-Review+1
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Change subject: mb/google/brya/var/trulo: Configure GPIO pins for ramstage
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Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/riven: Add Fn key scancode
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/20320250_cc2a078e?us… :
PS2, Line 8:
> Should the first letter in the commit summary be capitalized? If so, I need to update all the commit […]
Done
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Change subject: soc/intel/common/intelblocks/gpio.h: Allow specifying the pad ownership
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83315/comment/b4c0ed50_5e586e65?us… :
PS7, Line 124: uint16_t pad_own_reg_0; /* offset to Pad Ownership Reg 0 */
> it would be great if adding some comments for pad_own_reg_0 and host_own_reg_0 here.
Done
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Hello Jérémy Compostella, Paul Menzel, Shuo Liu, build bot (Jenkins), جوكر الطويل,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83314?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
......................................................................
soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/8
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