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Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> @krishna.p.bhat.d@intel. […]
Yes, this command is supported on both Lite SKU and Consumer SKU.
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Change subject: ec/starlabs/merlin: Remove cezanne-desktop variant
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Change subject: intel/alderlake: Add helper functions for Power Management
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Patch Set 11:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/863399ac_c2fd6d92?us… :
PS7, Line 504: ctl = ASPM_AUTO;
> So before this change unset in the devicetree meant `auto`. After this […]
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Change subject: i2c/drivers/generic: Add support for including a CDM
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Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81409/comment/198a2c04_dc4aee12?us… :
PS5, Line 13: rotating the device
: and checking the orientation is correct
> Yes, the horizontal axis was inverted. […]
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Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
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Patch Set 4: Code-Review+2
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
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Patch Set 9:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/aa04626f_d867dd17?us… :
PS7, Line 8: /* Select Bank 0 to allow writing to VBNV. */
> from the comment, one might infer that the value `0` passed to `cmos_init()` is for bank selection, […]
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Hello Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Karthik Ramasubramanian, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.
To fix the problem, define vbnv_platform_init_cmos() to call
cmos_init(0), which will configure the Register A and therefore allow
saving VBNV to CMOS in verstage.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/amd/common/vboot/vbnv_cmos.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/9
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 7:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/f61ae867_dbc478b5?us… :
PS4, Line 3: Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
> I've replaced FSP headers with the latest one.
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