Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.
Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS19:
> One thing to mention, if you are tracking test results from : https://qa.coreboot.org/job/coreboot-gerrit/261140/testReport/junit/(root)/…
>
> This is expected to fail,since the PTL SOC Kconfig will unment few dependencies, which will be the part of upcoming next stages of build. Although, to make fatcat Kconfig updated, i have verified it to be building correctly, while using all the required PTL SOC Kconfigs.
there is no harm to add minimal required Kconfig with initial CL. You can call it initial patch to boot PTL upto bootblock.
my only request is that, each SoC code should be build-able against a mainboard hence, we have fatcat mainboard added initially.
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Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83667?usp=email )
Change subject: src: Enable config to determine eSOL status
......................................................................
src: Enable config to determine eSOL status
The patch adds a config MAINBOARD_HAD_EARLY_SIGN_OF_LIFE to determine
whether eSOL is enabled.
BUG=NA
TEST=Able to build google/rex and google/tvviks
Change-Id: I68aca8033cf843e8a569339ab1af85fab104b36a
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/device/Kconfig
M src/soc/intel/meteorlake/Kconfig
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/83667/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 243e23e..3cb544c 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -52,6 +52,11 @@
Selected by mainboards whose graphics initialization depends on VGA OpROM.
coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX.
+config MAINBOARD_HAS_EARLY_SIGN_OF_LIFE
+ def_bool n
+ help
+ Enabled if the platform has an early sign of life feature.
+
config MAINBOARD_HAS_LIBGFXINIT
def_bool n
help
@@ -60,6 +65,7 @@
config MAINBOARD_HAS_EARLY_LIBGFXINIT
def_bool n
+ select MAINBOARD_HAS_EARLY_SIGN_OF_LIFE
help
Selected by mainboards that implement early (cache-as-ram
stage) support of `libgfxinit`. Usually this requires a list
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index ec8c318..8fe7930 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -461,6 +461,7 @@
bool
default y if !SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON
depends on MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_EARLY_SIGN_OF_LIFE
select VBT_CBFS_COMPRESSION_DEFAULT_LZ4
help
Enable the FSP-M Sign-of-Life feature to display a
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83620?usp=email )
Change subject: mb/starlabs/starbook/rpl: Don't set tcss_aux_ori
......................................................................
mb/starlabs/starbook/rpl: Don't set tcss_aux_ori
Not setting tcss_aux_ori in devicetree is the same as
setting it to zero so remove it.
Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
1 file changed, 1 insertion(+), 3 deletions(-)
Approvals:
Felix Held: Looks good to me, approved
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 7a3f9fb..c7b8738 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -57,9 +57,7 @@
end
end
device ref tbt_pcie_rp0 on end
- device ref tcss_xhci on
- register "tcss_aux_ori" = "0"
- end
+ device ref tcss_xhci on end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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Felix Held has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83620?usp=email )
Change subject: mb/starlabs/starbook/rpl: Don't set tcss_aux_ori
......................................................................
Patch Set 2: Code-Review+2
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