Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83663?usp=email )
Change subject: mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard
......................................................................
mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard
This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.
This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.
Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
CNVi WLAN has been removed.
This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/mainboard/google/brya/variants/orisa/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 9e6378f..f048dbb 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -15,7 +15,8 @@
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
- register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
+ # USB 2.0 Port #10 must be used for integrated BT with Intel CNVi
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 14324d3..80e5cf3 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -91,7 +91,6 @@
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Gerrit-Change-Number: 83663
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83651?usp=email )
Change subject: arch/arm64/armv8/mmu: Add missing header arch/barrier.h
......................................................................
arch/arm64/armv8/mmu: Add missing header arch/barrier.h
Also take the chance to sort the headers.
BUG=none
TEST=none
BRANCH=none
Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83651
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/arch/arm64/armv8/mmu.c
1 file changed, 4 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
Elyes Haouas: Looks good to me, approved
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 6105f9a..0f84146 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -5,10 +5,11 @@
#include <string.h>
#include <symbols.h>
-#include <console/console.h>
-#include <arch/mmu.h>
-#include <arch/lib_helpers.h>
+#include <arch/barrier.h>
#include <arch/cache.h>
+#include <arch/lib_helpers.h>
+#include <arch/mmu.h>
+#include <console/console.h>
/* This just caches the next free table slot (okay to do since they fill up from
* bottom to top and can never be freed up again). It will reset to its initial
--
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Gerrit-Change-Id: I9d487a40d0c58c6458b8b7d32b6401093fa417e7
Gerrit-Change-Number: 83651
Gerrit-PatchSet: 3
Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr>
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83654?usp=email )
Change subject: mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
......................................................................
mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Trulo variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:355384185
TEST=Able to enter S0ix on Trulo eMMC sku after disabling UFS
during boot path.
Able to grep below debug prints while booting the eMMC sku.
[INFO ] FW_CONFIG value from CBI is 0x20000000
[INFO ] Disabling UFS controllers
...
[INFO ] fw_config match found: STORAGE=STORAGE_EMMC
Change-Id: I06a84fa8c3843edae5932e19d394b18b72ace422
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83654
Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Amanda Hwang: Looks good to me, approved
Dinesh Gehlot: Looks good to me, approved
Eric Lai: Looks good to me, approved
David Wu: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index dfbd291..ec4cab4 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -554,6 +554,7 @@
select SOC_INTEL_TWINLAKE
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
+ select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
config BOARD_GOOGLE_ULDREN
select BOARD_GOOGLE_BASEBOARD_NISSA
--
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Attention is currently required from: Bao Zheng, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Zheng Bao.
Jon Murphy has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/83646?usp=email )
Change subject: mb/google/skyrim: Combine the variants function
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83646/comment/25696771_16eb1c73?us… :
PS1, Line 9: BUG=b:346716300
I don't understand how this change relates to this bug
File src/mainboard/google/skyrim/variants/baseboard/port_descriptors_combo.c:
PS1:
> having two port_descriptors files in the baseboard doesn't make much sense to me. […]
Agree that having duplicate code is not a good thing. I am a little hesitant about this change. I agree with Matt that having two files starts to feel confusing, but I also think naming things combo gets confusing since each variant needs to define the dxio descriptors and it's arbitrary what combo means. Unlikely that either of these variants would change, but they do differ from the rest.
The other variants have SD, NVMe, and WLAN, maybe rather than common you could make a WLAN_EMMC config and use a kconfig as Matt suggested.
In general I want to make sure it's clear what's happening, that we avoid escapes in the future, and agree that we should limit redundant copy/paste code.
In addition to the variant function, having the dxio descriptors guarded by a config and/or in a separate file avoids wasted memory allocation for a second unused array.
--
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