coreboot-gerrit July 2024

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[S] Change in coreboot[main]: i2c/drivers/generic: Add support for including a CDM
by Angel Pons (Code Review) 27 Jul '24

27 Jul '24

Attention is currently required from: Matt DeVillier, Paul Menzel, Sean Rhodes. Angel Pons has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81409?usp=email ) Change subject: i2c/drivers/generic: Add support for including a CDM ...................................................................... Patch Set 9: (3 comments) File src/drivers/i2c/generic/chip.h: https://review.coreboot.org/c/coreboot/+/81409/comment/7e68993a_7e6ab8e8?us… : PS9, Line 98: bool has_cdm; : int cdm_index; If a zero value is not valid, the boolean isn't needed: ```suggestion enum { CDM_NOT_PRESENT = 0, CDM_ROT_90 = 1, CDM_ROT_180 = 2, CDM_ROT_270 = 3, CDM_ROT_0 = 4, CDM_ROT_90_INVERT = 5, CDM_ROT_180_INVERT = 6, CDM_ROT_270_INVERT = 7, CDM_ROT_0_INVERT = 8, } cdm_index; ``` The acpigen magic would be skipped if `cdm_index` equals `CDM_NOT_PRESENT` (the default for unspecified devicetree settings) File src/drivers/i2c/generic/generic.c: https://review.coreboot.org/c/coreboot/+/81409/comment/5ba1298b_f98b407d?us… : PS9, Line 170: acpigen_write_method("_CDM", 1); Could this be a Name instead? Or does it need to be a Method? https://review.coreboot.org/c/coreboot/+/81409/comment/576bebdb_c8adbbae?us… : PS9, Line 171: + Any reason not to use a bitwise OR? -- To view, visit https://review.coreboot.org/c/coreboot/+/81409?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b Gerrit-Change-Number: 81409 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 27 Jul 2024 11:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/superiotool/fintek: Add f81966 register table
by Angel Pons (Code Review) 27 Jul '24

27 Jul '24

Attention is currently required from: Maxim. Angel Pons has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83019?usp=email ) Change subject: util/superiotool/fintek: Add f81966 register table ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Gerrit-Change-Number: 83019 Gerrit-PatchSet: 17 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Sat, 27 Jul 2024 11:11:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/superiotool/fintek: Add f81866 register table
by Angel Pons (Code Review) 27 Jul '24

27 Jul '24

Attention is currently required from: Felix Held, Felix Singer, Martin Roth, Maxim, Michał Żygowski, Paul Menzel. Angel Pons has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83004?usp=email ) Change subject: util/superiotool/fintek: Add f81866 register table ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Gerrit-Change-Number: 83004 Gerrit-PatchSet: 18 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Jul 2024 11:11:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: util/superiotool: Add extra selectors support
by Angel Pons (Code Review) 27 Jul '24

27 Jul '24

Attention is currently required from: Felix Held, Maxim, Paul Menzel. Angel Pons has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83196?usp=email ) Change subject: util/superiotool: Add extra selectors support ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Gerrit-Change-Number: 83196 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 27 Jul 2024 11:11:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Angel Pons (Code Review) 27 Jul '24

27 Jul '24

Attention is currently required from: Alexander Couzens, Cleyton Silva, Keith Hui. Angel Pons has posted comments on this change by Cleyton Silva. ( https://review.coreboot.org/c/coreboot/+/83670?usp=email ) Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... Patch Set 1: Code-Review+1 (24 comments) Patchset: PS1: Welcome to coreboot! Commit Message: https://review.coreboot.org/c/coreboot/+/83670/comment/d1282377_c83b0844?us… : PS1, Line 13: 2MB+4MB Hmmm, usually the larger chip is the first one. Could you please check? I believe inteltool's dump option would answer this question, if you have a full firmware dump. https://review.coreboot.org/c/coreboot/+/83670/comment/6fb84b74_e905652f?us… : PS1, Line 20: - All USB ports : - USB 2.0 headers "All USB ports" would already include "USB 2.0 headers", I believe. Was any USB port/header/connector not tested? https://review.coreboot.org/c/coreboot/+/83670/comment/59760835_3dd1e926?us… : PS1, Line 26: - Audio If the `F_AUDIO` header is untested, I imagine this refers to the rear audio jacks. Would be nice to specify https://review.coreboot.org/c/coreboot/+/83670/comment/73a013b4_12a0af4f?us… : PS1, Line 43: - Internal flashing : - External flashing (in-circuit) Flashing internally should be possible when running coreboot. Could you please describe the errors you get in each case? Also, how was the board flashed? File src/mainboard/lenovo/ih61m/Kconfig: https://review.coreboot.org/c/coreboot/+/83670/comment/5a95f317_387a5295?us… : PS1, Line 27: config DRAM_RESET_GATE_GPIO : int : default 60 Default, can be dropped. https://review.coreboot.org/c/coreboot/+/83670/comment/e784873a_52fe2775?us… : PS1, Line 31: config USBDEBUG_HCD_INDEX : int : default 2 #top usb port located next to vga connector : #default 1 #yellow upper header F_USB1 The `int` type is not needed, and I would refactor the comments a bit: ```suggestion # HCD 1: yellow upper header F_USB1 # HCD 2: top USB port located next to VGA connector config USBDEBUG_HCD_INDEX default 2 ``` Defaulting to the connector on the back panel is very reasonable (it doesn't require extra hardware to be used) File src/mainboard/lenovo/ih61m/Kconfig.name: https://review.coreboot.org/c/coreboot/+/83670/comment/34efbda6_3f9a743d?us… : PS1, Line 1: config BOARD_LENOVO_IH61MV1 : bool "IH61M Ver:1.0" : : config BOARD_LENOVO_IH61MV4 : bool "IH61M Ver:4.2" nit-pick: Add an extra underscore to the Kconfig symbols to separate the model and the version? ```suggestion config BOARD_LENOVO_IH61M_V1 bool "IH61M Ver:1.0" config BOARD_LENOVO_IH61M_V4 bool "IH61M Ver:4.2" ``` File src/mainboard/lenovo/ih61m/acpi_tables.c: PS1: You can delete this file. autoport generates it by default but it only makes a difference if other code uses these GNVS values. File src/mainboard/lenovo/ih61m/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83670/comment/de293a66_c5f03988?us… : PS1, Line 1: # SPDX-License-Identifier: GPL-2.0-or-later : chip northbridge/intel/sandybridge nit-pick: Add a blank line after the license header? ```suggestion # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge ``` https://review.coreboot.org/c/coreboot/+/83670/comment/5e953c89_d2379311?us… : PS1, Line 6: device ref host_bridge on end # Host bridge Devices that are already on/off in the chipset devicetree [1] can be omitted. Here, the host bridge is already enabled. [1]: https://github.com/coreboot/coreboot/blob/main/src/northbridge/intel/sandyb… https://review.coreboot.org/c/coreboot/+/83670/comment/e3d07e84_ea6fd2c1?us… : PS1, Line 10: register "docking_supported" = "0" Generally, a devicetree "register" that is set to a zero value can be omitted (it is already zero by default). This line can be omitted https://review.coreboot.org/c/coreboot/+/83670/comment/9839224f_046973bd?us… : PS1, Line 14: register "gen4_dec" = "0x00000000" : register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" Zero by default, can also be omitted https://review.coreboot.org/c/coreboot/+/83670/comment/5e62c1aa_cf8517e8?us… : PS1, Line 37: device ref mei1 on end : device ref me_ide_r off end : device ref me_kt off end Same state as chipset devicetree, can be omitted. https://review.coreboot.org/c/coreboot/+/83670/comment/008da120_e377072c?us… : PS1, Line 41: device ref gbe on end This device is only used with a special kind of Intel GbE controllers. Looks like this board uses a Realtek GbE controller instead, so this line can be removed. https://review.coreboot.org/c/coreboot/+/83670/comment/72bcbc7c_2cd5f947?us… : PS1, Line 43: device ref pcie_rp1 on end : device ref pcie_rp4 on end # PCIEX1_1 : device ref pcie_rp5 on end # PCIEX1_2 : device ref pcie_rp6 on end Do you know what the rest of PCIe ports are used for? From the V1.0 schematics, looks like the mapping is as follows: ```suggestion device ref pcie_rp4 on end # PCIEX1_1 slot device ref pcie_rp5 on end # PCIEX1_2 slot device ref pcie_rp6 on end # Realtek RTL8111E GbE ``` https://review.coreboot.org/c/coreboot/+/83670/comment/cd8031a2_6b8d4c4c?us… : PS1, Line 67: io 0x60 = 0x02f8 nit-pick: Use consistent style across the file, e.g. ```suggestion io 0x60 = 0x2f8 ``` https://review.coreboot.org/c/coreboot/+/83670/comment/31a5bd41_d60f0ec1?us… : PS1, Line 107: device ref sata2 off end # SATA (Legacy) Already disabled in chipset devicetree, can remove from here https://review.coreboot.org/c/coreboot/+/83670/comment/f788367e_e89ecc24?us… : PS1, Line 108: device ref smbus on end # SMBus Already enabled in chipset devicetree, can remove from here File src/mainboard/lenovo/ih61m/early_init.c: https://review.coreboot.org/c/coreboot/+/83670/comment/89f7ae5e_3961f6ff?us… : PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ : #include <bootblock_common.h> Nit-pick: Blank line after license header: ```suggestion /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> ``` File src/mainboard/lenovo/ih61m/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/83670/comment/16f03323_65b25afe?us… : PS1, Line 11: ports : constant Port_List := : (HDMI1, : HDMI2, : HDMI3, : Analog, : others => Disabled); V1.0 schematics say DVI-D is on digital output D (HDMI3): ```suggestion ports : constant Port_List := (HDMI3, -- DVI-D Analog, -- VGA others => Disabled); ``` File src/mainboard/lenovo/ih61m/hda_verb.c: https://review.coreboot.org/c/coreboot/+/83670/comment/025f808f_ac7aaa75?us… : PS1, Line 21: 0x80862805, /* Codec Vendor / Device ID: Intel */ : 0x80860101, /* Subsystem ID */ : 4, /* Number of 4 dword sets */ : AZALIA_SUBVENDOR(3, 0x80860101), : AZALIA_PIN_CFG(3, 0x05, 0x18560010), : AZALIA_PIN_CFG(3, 0x06, 0x18560020), : AZALIA_PIN_CFG(3, 0x07, 0x18560030), This is for the iGPU's audio outputs. If this board doesn't have HDMI or DP outputs, this is irrelevant (neither DVI nor VGA support audio) https://review.coreboot.org/c/coreboot/+/83670/comment/0b4b7186_e71b0828?us… : PS1, Line 28: nit-pick: drop blank line File src/mainboard/lenovo/ih61m/mainboard.c: https://review.coreboot.org/c/coreboot/+/83670/comment/340c5338_4f5ca01c?us… : PS1, Line 10: beep(2500, 100); This is not mainboard-specific. Instead, consider making a separate change that adds a Kconfig option to enable beeping on boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 1 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Cleyton Silva <pokecleyton(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sat, 27 Jul 2024 11:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/lenovo: Add IH61M mainboard
by Cleyton Silva (Code Review) 27 Jul '24

27 Jul '24

Cleyton Silva has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83670?usp=email ) Change subject: mb/lenovo: Add IH61M mainboard ...................................................................... mb/lenovo: Add IH61M mainboard This is based on the autoport output with some manual corrections. This mainboard is used in several Lenovo desktop models. It comes in two versions, Ver:1.0 and Ver:4.2. Version 1.0 has only a 4MB SPI chip and 4.2 has a 2MB+4MB array. The VBT was obtained with "intelvbttool -l -v data.vbt" from the vendor firmware version "F1KT54AUS". Works: - Ivy/Sandy Bridge CPUs - All USB ports - USB 2.0 headers - USB EHCI debug - All SATA ports - VGA - Ethernet - Audio - PCIe x16 slot - PCIe x1 slots - S3 suspend/resume - Libgfxinit - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) Unknown/untested: - DVI-D - PS/2 - COM1/COM2 - LPT header - F_AUDIO header - LPC_DEBUG header Does not work: - Internal flashing - External flashing (in-circuit) Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Signed-off-by: Cleyton Silva <pokecleyton(a)gmail.com> --- A src/mainboard/lenovo/ih61m/Kconfig A src/mainboard/lenovo/ih61m/Kconfig.name A src/mainboard/lenovo/ih61m/Makefile.mk A src/mainboard/lenovo/ih61m/acpi/ec.asl A src/mainboard/lenovo/ih61m/acpi/platform.asl A src/mainboard/lenovo/ih61m/acpi/superio.asl A src/mainboard/lenovo/ih61m/acpi_tables.c A src/mainboard/lenovo/ih61m/board_info.txt A src/mainboard/lenovo/ih61m/cmos.default A src/mainboard/lenovo/ih61m/cmos.layout A src/mainboard/lenovo/ih61m/data.vbt A src/mainboard/lenovo/ih61m/devicetree.cb A src/mainboard/lenovo/ih61m/dsdt.asl A src/mainboard/lenovo/ih61m/early_init.c A src/mainboard/lenovo/ih61m/gma-mainboard.ads A src/mainboard/lenovo/ih61m/gpio.c A src/mainboard/lenovo/ih61m/hda_verb.c A src/mainboard/lenovo/ih61m/mainboard.c 18 files changed, 607 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83670/1 diff --git a/src/mainboard/lenovo/ih61m/Kconfig b/src/mainboard/lenovo/ih61m/Kconfig new file mode 100644 index 0000000..3739798 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/Kconfig @@ -0,0 +1,35 @@ +if BOARD_LENOVO_IH61MV1 || BOARD_LENOVO_IH61MV4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_IH61MV1 #W25Q32(4MB) + select BOARD_ROMSIZE_KB_6144 if BOARD_LENOVO_IH61MV4 #W25Q32+W25Q16(6MB) + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "lenovo/ih61m" + +config MAINBOARD_PART_NUMBER + default "IH61M Ver:1.0" if BOARD_LENOVO_IH61MV1 + default "IH61M Ver:4.2" if BOARD_LENOVO_IH61MV4 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config USBDEBUG_HCD_INDEX + int + default 2 #top usb port located next to vga connector + #default 1 #yellow upper header F_USB1 +endif diff --git a/src/mainboard/lenovo/ih61m/Kconfig.name b/src/mainboard/lenovo/ih61m/Kconfig.name new file mode 100644 index 0000000..34ec1cb --- /dev/null +++ b/src/mainboard/lenovo/ih61m/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_LENOVO_IH61MV1 + bool "IH61M Ver:1.0" + +config BOARD_LENOVO_IH61MV4 + bool "IH61M Ver:4.2" diff --git a/src/mainboard/lenovo/ih61m/Makefile.mk b/src/mainboard/lenovo/ih61m/Makefile.mk new file mode 100644 index 0000000..d98fc7a --- /dev/null +++ b/src/mainboard/lenovo/ih61m/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/ih61m/acpi/ec.asl b/src/mainboard/lenovo/ih61m/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/lenovo/ih61m/acpi/platform.asl b/src/mainboard/lenovo/ih61m/acpi/platform.asl new file mode 100644 index 0000000..7b1b2b2 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/lenovo/ih61m/acpi/superio.asl b/src/mainboard/lenovo/ih61m/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/ih61m/acpi_tables.c b/src/mainboard/lenovo/ih61m/acpi_tables.c new file mode 100644 index 0000000..6296106 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/acpi_tables.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/ih61m/board_info.txt b/src/mainboard/lenovo/ih61m/board_info.txt new file mode 100644 index 0000000..dd79d41 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/lenovo/ih61m/cmos.default b/src/mainboard/lenovo/ih61m/cmos.default new file mode 100644 index 0000000..2fc74aa --- /dev/null +++ b/src/mainboard/lenovo/ih61m/cmos.default @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=128M diff --git a/src/mainboard/lenovo/ih61m/cmos.layout b/src/mainboard/lenovo/ih61m/cmos.layout new file mode 100644 index 0000000..d3676ae --- /dev/null +++ b/src/mainboard/lenovo/ih61m/cmos.layout @@ -0,0 +1,88 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: mainboard-specific + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/lenovo/ih61m/data.vbt b/src/mainboard/lenovo/ih61m/data.vbt new file mode 100644 index 0000000..1516f9a --- /dev/null +++ b/src/mainboard/lenovo/ih61m/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/ih61m/devicetree.cb b/src/mainboard/lenovo/ih61m/devicetree.cb new file mode 100644 index 0000000..3e61e53 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/devicetree.cb @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + device domain 0 on + subsystemid 0x17aa 0x308c inherit + device ref host_bridge on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a31" + register "gen2_dec" = "0x00fc0a21" + register "gen3_dec" = "0x00fc0a01" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 1, 0}, + {1, 1, 0}, + {1, 1, 1}, + {1, 1, 1}, + {1, 9, 2}, + {1, 9, 2}, + {0, 6, 3}, + {0, 6, 3}, + {1, 0x55f, 4}, + {1, 0x55f, 4}, + {1, 6, 6}, + {1, 6, 5}, + {0, 6, 5}, + {0, 6, 6}, + }" + device ref mei1 on end + device ref me_ide_r off end + device ref me_kt off end + device ref ehci2 on end + device ref gbe on end + device ref hda on end + device ref pcie_rp1 on end + device ref pcie_rp4 on end # PCIEX1_1 + device ref pcie_rp5 on end # PCIEX1_2 + device ref pcie_rp6 on end + device ref ehci1 on end + device ref pci_bridge on end + device ref lpc on + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x1c = 0x80 + irq 0x27 = 0xc0 + irq 0x2a = 0x62 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.8 off end # WDT1 + device pnp 2e.308 on # GPIO base + io 0x60 = 0x0 + irq 0xf0 = 0x3e # + GPIO1 direction + irq 0xf1 = 0xde # + GPIO1 value + end + device pnp 2e.a on # ACPI + irq 0xe0 = 0x01 + irq 0xe3 = 0x14 + irq 0xe4 = 0x10 # + enable 3VSBSW# + irq 0xe6 = 0x4c + irq 0xe9 = 0x02 + irq 0xf0 = 0x20 # + pin 70 = 3VSBSW + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0x0000 + irq 0x70 = 0 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device ref sata1 on end # SATA (AHCI) + device ref sata2 off end # SATA (Legacy) + device ref smbus on end # SMBus + end + end +end diff --git a/src/mainboard/lenovo/ih61m/dsdt.asl b/src/mainboard/lenovo/ih61m/dsdt.asl new file mode 100644 index 0000000..f432696 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/ih61m/early_init.c b/src/mainboard/lenovo/ih61m/early_init.c new file mode 100644 index 0000000..d8da88f --- /dev/null +++ b/src/mainboard/lenovo/ih61m/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1c, 0x83); + pnp_write_config(GLOBAL_DEV, 0x24, 0x30); + pnp_write_config(GLOBAL_DEV, 0x27, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x20); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + pnp_set_logical_device(SERIAL_DEV); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/lenovo/ih61m/gma-mainboard.ads b/src/mainboard/lenovo/ih61m/gma-mainboard.ads new file mode 100644 index 0000000..0cdc709 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/ih61m/gpio.c b/src/mainboard/lenovo/ih61m/gpio.c new file mode 100644 index 0000000..acb35d8 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/gpio.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/ih61m/hda_verb.c b/src/mainboard/lenovo/ih61m/hda_verb.c new file mode 100644 index 0000000..7ff6b19 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x00000000, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0, 0x19, 0x02a19831), + AZALIA_PIN_CFG(0, 0x1a, 0x0181343f), + AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/ih61m/mainboard.c b/src/mainboard/lenovo/ih61m/mainboard.c new file mode 100644 index 0000000..b8004f0 --- /dev/null +++ b/src/mainboard/lenovo/ih61m/mainboard.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <pc80/i8254.h> + +static void mainboard_final(void *unused) +{ +beep(2500, 100); +} + +static void mainboard_enable(struct device *dev) +{ + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/83670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7387bd46113e85fd00b17374ec4dee8e23b4e2c Gerrit-Change-Number: 83670 Gerrit-PatchSet: 1 Gerrit-Owner: Cleyton Silva <pokecleyton(a)gmail.com>

1 0

[XS] Change in coreboot[main]: Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity"
by Subrata Banik (Code Review) 27 Jul '24

27 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83658?usp=email ) Change subject: Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity" ...................................................................... Revert "soc/intel/adl: Guard TWL SoC missing UPDs for build integrity" This reverts commit 59ee65d271c7c617bcc240019231da4f0bd04db6. Reason for revert: - Usb4CmMode & CnviWifiCore Upds are available starting with TWL FSP version v5222.01. Therefore, no special handling is required. BUG=b:330654700 TEST=Able to build google/tivviks. Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83658 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: V Sowmya: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index d7b30c6..2cbf796 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -683,9 +683,7 @@ s_cfg->UsbTcPortEn |= BIT(i); } -#if !CONFIG(SOC_INTEL_TWINLAKE) s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); -#endif } static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, @@ -833,9 +831,7 @@ const struct soc_intel_alderlake_config *config) { /* CNVi */ -#if !CONFIG(SOC_INTEL_TWINLAKE) s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); -#endif s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); s_cfg->CnviBtCore = config->cnvi_bt_core; s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; -- To view, visit https://review.coreboot.org/c/coreboot/+/83658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c74ec5b9924e88a26984fe8d3275ba80edb14ab Gerrit-Change-Number: 83658 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10
by Subrata Banik (Code Review) 27 Jul '24

27 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83666?usp=email ) Change subject: mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10 ...................................................................... mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10 This change adds a new USB2 Bluetooth device configuration on Port 10 for the Trulo variant. * A new `drivers/usb/acpi` chip is added with: * `desc` set to "USB2 Bluetooth" * `type` set to "UPC_TYPE_INTERNAL" * `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" * `device` referencing `usb2_port10` BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index a9be57c..3ae9f85 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -446,6 +446,12 @@ device ref usb2_port5 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/83666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba Gerrit-Change-Number: 83666 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/trulo: Remove unused Bluetooth device
by Subrata Banik (Code Review) 27 Jul '24

27 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83665?usp=email ) Change subject: mb/google/brya/var/trulo: Remove unused Bluetooth device ...................................................................... mb/google/brya/var/trulo: Remove unused Bluetooth device This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Trulo variant. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83665 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rishika Raj <rishikaraj(a)google.com> --- M src/mainboard/google/brya/variants/trulo/overridetree.cb 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Rishika Raj: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 8f63cc3..a9be57c 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -87,7 +87,6 @@ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 (DB) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 (MLB) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB) @@ -447,13 +446,6 @@ device ref usb2_port5 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" - device ref usb2_port6 on end - end - chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/83665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9970274b9b1b1076a2f9d649d61c825cac71d0c7 Gerrit-Change-Number: 83665 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya/var/orisa: Remove unused Bluetooth device
by Subrata Banik (Code Review) 27 Jul '24

27 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83664?usp=email ) Change subject: mb/google/brya/var/orisa: Remove unused Bluetooth device ...................................................................... mb/google/brya/var/orisa: Remove unused Bluetooth device This change removes the configuration for the unused USB2 Port 6 (index 5) and its associated Bluetooth device on the Orisa variant. It also cleans up a redundant newline before the `serial_io_i2c_mode` definition. BUG=b:351976770 TEST=Builds successfully for google/orisa. Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83664 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rishika Raj <rishikaraj(a)google.com> --- M src/mainboard/google/brya/variants/orisa/overridetree.cb 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Rishika Raj: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 80e5cf3..543a667 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -88,7 +88,6 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 @@ -126,7 +125,6 @@ .vnn_icc_max_ma = 500, }" - register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -447,13 +445,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" - device ref usb2_port6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83664?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf1ff442530ad2263ad0b58829e5c7b2ce544439 Gerrit-Change-Number: 83664 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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