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Code-Review+1 by Angel Pons
Change subject: i2c/drivers/generic: Add support for including a CDM
......................................................................
i2c/drivers/generic: Add support for including a CDM
Chip Direct Mapping is exclusive to Windows; it allows specifying the
position where a chip is mounted. There are 8 positions and a _CDM
method should return 0xabcd0X, where X is the position.
Tested by booting Windows 11 on the StarLite Mk V, rotating the device
and checking the orientation is correct, where previously, it was
inverted.
Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/i2c/generic/chip.h
M src/drivers/i2c/generic/generic.c
2 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81409/11
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Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
intel/alderlake: Add helper functions for Power Management
Clock Power Management, ASPM and L1 Substates have been
configured the same way since Skylake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.
Despite the UPDs remaining the same since Skylake, this is not the
case for Alder Lake, Raptor Lake and Meteor Lake.
Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.
On Comet Lake, this results in the correct configuration, verified
with the lspci command:
```
LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On Raptor Lake:
```
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```
Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.
Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.
Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 88 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/24
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Change subject: i2c/drivers/generic: Add support for including a CDM
......................................................................
Patch Set 10: Code-Review+2
(1 comment)
File src/drivers/i2c/generic/generic.c:
https://review.coreboot.org/c/coreboot/+/81409/comment/cfd23579_6440ee1c?us… :
PS9, Line 170: acpigen_write_method("_CDM", 1);
> Has to be method, assume driver is badly written 😊
Ack
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Change subject: i2c/drivers/generic: Add support for including a CDM
......................................................................
Patch Set 10:
(3 comments)
File src/drivers/i2c/generic/chip.h:
https://review.coreboot.org/c/coreboot/+/81409/comment/af63a1c8_75b690f4?us… :
PS9, Line 98: bool has_cdm;
: int cdm_index;
> Redundancy. I wasn't feeling great when writing that. […]
Done
File src/drivers/i2c/generic/generic.c:
https://review.coreboot.org/c/coreboot/+/81409/comment/0c9d6e21_8083701c?us… :
PS9, Line 170: acpigen_write_method("_CDM", 1);
> Could this be a Name instead? Or does it need to be a Method?
Has to be method, assume driver is badly written 😊
https://review.coreboot.org/c/coreboot/+/81409/comment/4223250b_dd8fea83?us… :
PS9, Line 171: +
> Any reason not to use a bitwise OR?
Done
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Change subject: soc/intel/alderlake: Hook up PCI Power Management to option API
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81906/comment/45d620ed_b2665922?us… :
PS8, Line 7: PCI
nit: PCIe
https://review.coreboot.org/c/coreboot/+/81906/comment/125d0102_cd655c96?us… :
PS8, Line 9: PCICLK_PM
Can't find this symbol
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81906/comment/8ceb20be_90c40572?us… :
PS8, Line 535: bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM));
: bool pciexp_aspm = get_uint_option("pciexp_aspm", CONFIG(PCIEXP_ASPM));
: bool pciexp_l1_sub_state = get_uint_option("pciexp_l1_sub_state",
: CONFIG(PCIEXP_L1_SUB_STATE));
I would prefer to only call the option API once per option
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81409?usp=email
to look at the new patch set (#10).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: i2c/drivers/generic: Add support for including a CDM
......................................................................
i2c/drivers/generic: Add support for including a CDM
Chip Direct Mapping is exclusive to Windows; it allows specifying the
position where a chip is mounted. There are 8 positions and a _CDM
method should return 0xabcd0X, where X is the position.
Tested by booting Windows 11 on the StarLite Mk V, rotating the device
and checking the orientation is correct, where previously, it was
inverted.
Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/i2c/generic/chip.h
M src/drivers/i2c/generic/generic.c
2 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81409/10
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Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................
Patch Set 23: Code-Review+1
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