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Change subject: mb/emulation/qemu-sbsa: Generate PPTT ACPI table
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/emulation/qemu-sbsa/pptt.c:
https://review.coreboot.org/c/coreboot/+/79108/comment/d127ec2d_61e01f19?us… :
PS7, Line 9: #define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type
: #define CLUSTER_FLAGS 0x11 // physical package, ID invalid, no thread, no leaf, identical impl.
: #define CORE_FLAGS 0x1a // no physical package, ID valid, no thread, leaf, identical impl.
:
: #define CACHE_ATTR_TYPE_DATA (0)
: #define CACHE_ATTR_TYPE_INSTRUCTION (0x1 << 2)
: #define CACHE_ATTR_TYPE_UNIFIED (0x1 << 3)
> Would it make sense to have this in the header exposing acpi_get_pptt_topology?
The first three definitions are rather mainboard specific. One could put the latter three in the acpi headers but I guess that would be a thing for another separate patch.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS19:
> Hi Subrata, yes there was a missing config "SOC_INTEL_COMMON", due to which kconfig build was gettin […]
One thing to mention, if you are tracking test results from : https://qa.coreboot.org/job/coreboot-gerrit/261140/testReport/junit/(root)/…
This is expected to fail,since the PTL SOC Kconfig will unment few dependencies, which will be the part of upcoming next stages of build. Although, to make fatcat Kconfig updated, i have verified it to be building correctly, while using all the required PTL SOC Kconfigs.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83641?usp=email )
Change subject: arch/riscv: Remove opensbi submodule includes
......................................................................
arch/riscv: Remove opensbi submodule includes
Currently we include a header file from the opensbi submodule.
That causes some issues, since we merge outside code with our own.
Most recently there have been made attempts to make the coreboot
codebase C23 ready. The code that we include from opensbi however causes
the build to fail, since it is not C23 ready.
This patch effectivily detaches the coreboot codebase from the opensbi
codebase and just copies the structure and definitions that we need from
opensbi into coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I9d8f85ee805bbbf2627ef419685440b37c15f906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83641
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/arch/riscv/Makefile.mk
M src/arch/riscv/opensbi.c
2 files changed, 34 insertions(+), 23 deletions(-)
Approvals:
Elyes Haouas: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk
index d5defea..6754c22 100644
--- a/src/arch/riscv/Makefile.mk
+++ b/src/arch/riscv/Makefile.mk
@@ -180,7 +180,6 @@
check-ramstage-overlap-files += $(OPENSBI_CBFS)
-CPPFLAGS_common += -I$(OPENSBI_SOURCE)/include
ramstage-y += opensbi.c
endif #CONFIG_RISCV_OPENSBI
diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
index bf26b22..36f2951 100644
--- a/src/arch/riscv/opensbi.c
+++ b/src/arch/riscv/opensbi.c
@@ -1,13 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* OpenSBI wants to make its own definitions for some of our compiler.h macros. */
-#undef __packed
-#undef __noreturn
-#undef __aligned
-
-#include <sbi/fw_dynamic.h>
#include <arch/boot.h>
-/* DO NOT INCLUDE COREBOOT HEADERS HERE */
+#include <arch/encoding.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#define FW_DYNAMIC_INFO_VERSION_2 2
+#define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f // "OSBI"
+
+/*
+ * structure passed to OpenSBI as 3rd argument
+ * NOTE: This structure may need to be updated when the OpenSBI submodule is updated.
+ */
+static struct __packed fw_dynamic_info {
+ unsigned long magic; // magic value "OSBI"
+ unsigned long version; // version number (2)
+ unsigned long next_addr; // Next booting stage address (payload address)
+ unsigned long next_mode; // Next booting stage mode (usually supervisor mode)
+ unsigned long options; // options for OpenSBI library
+ unsigned long boot_hart; // usually CONFIG_RISCV_WORKING_HARTID
+} info;
void run_opensbi(const int hart_id,
const void *fdt,
@@ -15,21 +27,21 @@
const void *payload,
const int payload_mode)
{
- struct fw_dynamic_info info = {
- .magic = FW_DYNAMIC_INFO_MAGIC_VALUE,
- .version = FW_DYNAMIC_INFO_VERSION_MAX,
- .next_mode = payload_mode,
- .next_addr = (uintptr_t)payload,
- .options = 0,
- .boot_hart = CONFIG_OPENSBI_FW_DYNAMIC_BOOT_HART,
- };
+ info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE,
+ info.version = FW_DYNAMIC_INFO_VERSION_2,
+ info.next_mode = payload_mode,
+ info.next_addr = (uintptr_t)payload,
+ info.options = 0,
+ info.boot_hart = CONFIG_OPENSBI_FW_DYNAMIC_BOOT_HART,
- csr_write(mepc, opensbi);
+ write_csr(mepc, opensbi); // set program counter to OpenSBI (jumped to with mret)
asm volatile (
- "mv a0, %0\n\t"
- "mv a1, %1\n\t"
- "mv a2, %2\n\t"
- "mret" :
- : "r"(hart_id), "r"(fdt), "r"(&info)
- : "a0", "a1", "a2");
+ "mv a0, %0\n\t"
+ "mv a1, %1\n\t"
+ "mv a2, %2\n\t"
+ "mret"
+ :
+ : "r"(hart_id), "r"(fdt), "r"(&info)
+ : "a0", "a1", "a2"
+ );
}
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: vc/intel/fsp: Update twinlake FSP headers from v5142.00 to v5222.01
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83404/comment/bfc0d5bc_bcc4792d?us… :
PS3, Line 7: vc/intel/fsp: Update twinlake FSP headers from v5142.00 to v5222.01
Maybe:
> vc/intel/fsp/twinlake: Update FSP headers from v5142.00 to v5222.01
https://review.coreboot.org/c/coreboot/+/83404/comment/75725c0a_38f82830?us… :
PS3, Line 9: twinlake
Twin Lake
https://review.coreboot.org/c/coreboot/+/83404/comment/a521a5fa_72b2c6d6?us… :
PS3, Line 12: - Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h
What do you mean by open?
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Change subject: security/intel/txt: Handle TPM properly when vboot enabled
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82695/comment/5ceecd59_04398657?us… :
PS4, Line 8:
Please elaborate.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 20:
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/3fe337c2_357f74bf?us… :
PS14, Line 67: ~1KiB)
> The minimum stack size requirement for FSP-M is 256KB.
how is this even possible when we have 512KB req for MTL FSP. wondering if this is bug in the doc where it follow some old recommendation with lacking of reality check.
> HOB Heap requirement is at least 128KB. The stack allocated by the bootloader must be large enough for both FSP-M as well as any other parent function calls that are still on the stack at the point when FspMemoryInit() is called. 512KiB is pretty good for FSP-M stack requirement in CAR.
Please get this clarified by FSP team and ensure to capture into the FSP integration guide.
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