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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 19:
(1 comment)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/ed896ded_27987cf0?us… :
PS8, Line 37: VTD_BASE_ADDRESS
> This indicates ADL and earlier, where this address was used for VTDBAR. In MTL-PTL it was updated as DMI3BAR. VTDBAR moved to a different address.
in summary the address has be updated and not the functionality
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83457?usp=email )
Change subject: commonlib/device_tree.c: Add read reg property helper
......................................................................
commonlib/device_tree.c: Add read reg property helper
Add a helper function to read the reg property from an unflattened
device tree.
It also factors out the common code into a new function called
`read_reg_prop`.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I7846eb8af390d709b0757262025cb819e9988699
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83457
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/commonlib/device_tree.c
M src/commonlib/include/commonlib/device_tree.h
2 files changed, 73 insertions(+), 26 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c
index 0ec6ea9..a8a64ec 100644
--- a/src/commonlib/device_tree.c
+++ b/src/commonlib/device_tree.c
@@ -59,10 +59,49 @@
return xzalloc(sizeof(struct device_tree_property));
}
+
+/*
+ * internal functions used by both unflattened and flattened device tree variants
+ */
+
+
+static size_t read_reg_prop(struct fdt_property *prop, u32 addr_cells, u32 size_cells,
+ struct device_tree_region regions[], size_t regions_count)
+{
+ // we found the reg property, no need to parse all regions in 'reg'
+ size_t count = prop->size / (4 * addr_cells + 4 * size_cells);
+ if (count > regions_count) {
+ printk(BIOS_ERR, "reg property has more entries (%zd) than regions array can hold (%zd)\n", count, regions_count);
+ count = regions_count;
+ }
+ if (addr_cells > 2 || size_cells > 2) {
+ printk(BIOS_ERR, "addr_cells (%d) or size_cells (%d) bigger than 2\n",
+ addr_cells, size_cells);
+ return 0;
+ }
+ uint32_t *ptr = prop->data;
+ for (int i = 0; i < count; i++) {
+ if (addr_cells == 1)
+ regions[i].addr = be32dec(ptr);
+ else if (addr_cells == 2)
+ regions[i].addr = be64dec(ptr);
+ ptr += addr_cells;
+ if (size_cells == 1)
+ regions[i].size = be32dec(ptr);
+ else if (size_cells == 2)
+ regions[i].size = be64dec(ptr);
+ ptr += size_cells;
+ }
+
+ return count; // return the number of regions found in the reg property
+}
+
+
/*
* Functions for picking apart flattened trees.
*/
+
static int fdt_skip_nops(const void *blob, uint32_t offset)
{
uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset);
@@ -203,32 +242,7 @@
return 0;
}
- // we found the reg property, now need to parse all regions in 'reg'
- size_t count = prop.size / (4 * addr_cells + 4 * size_cells);
- if (count > regions_count) {
- printk(BIOS_ERR, "reg property at node_offset: %x has more entries (%zd) than regions array can hold (%zd)\n", node_offset, count, regions_count);
- count = regions_count;
- }
- if (addr_cells > 2 || size_cells > 2) {
- printk(BIOS_ERR, "addr_cells (%d) or size_cells (%d) bigger than 2\n",
- addr_cells, size_cells);
- return 0;
- }
- uint32_t *ptr = prop.data;
- for (int i = 0; i < count; i++) {
- if (addr_cells == 1)
- regions[i].addr = be32dec(ptr);
- else if (addr_cells == 2)
- regions[i].addr = be64dec(ptr);
- ptr += addr_cells;
- if (size_cells == 1)
- regions[i].size = be32dec(ptr);
- else if (size_cells == 2)
- regions[i].size = be64dec(ptr);
- ptr += size_cells;
- }
-
- return count; // return the number of regions found in the reg property
+ return read_reg_prop(&prop, addr_cells, size_cells, regions, regions_count);
}
static u32 fdt_read_cell_props(const void *blob, u32 node_offset, u32 *addrcp, u32 *sizecp)
@@ -981,6 +995,37 @@
*/
/*
+ * dt_read_reg_prop reads the reg property inside a node
+ *
+ * @params node device tree node to read reg property from
+ * @params addr_cells number of cells used for one address
+ * @params size_cells number of cells used for one size
+ * @params regions all regions that are read inside the reg property are saved inside
+ * this array
+ * @params regions_count maximum number of entries that can be saved inside the regions array.
+ *
+ * Returns: Either 0 on error or returns the number of regions put into the regions array.
+ */
+size_t dt_read_reg_prop(struct device_tree_node *node, u32 addr_cells, u32 size_cells,
+ struct device_tree_region regions[], size_t regions_count)
+{
+ struct device_tree_property *prop;
+ bool found = false;
+ list_for_each(prop, node->properties, list_node) {
+ if (!strcmp("reg", prop->prop.name)) {
+ found = true;
+ break;
+ }
+ }
+
+ if (!found) {
+ printk(BIOS_DEBUG, "no reg property found\n");
+ return 0;
+ }
+ return read_reg_prop(&prop->prop, addr_cells, size_cells, regions, regions_count);
+}
+
+/*
* Read #address-cells and #size-cells properties from a node.
*
* @param node The device tree node to read from.
diff --git a/src/commonlib/include/commonlib/device_tree.h b/src/commonlib/include/commonlib/device_tree.h
index 81377fa..c15d7ae 100644
--- a/src/commonlib/include/commonlib/device_tree.h
+++ b/src/commonlib/include/commonlib/device_tree.h
@@ -147,6 +147,8 @@
/* Flatten a device tree into the buffer pointed to by dest. */
void dt_flatten(const struct device_tree *tree, void *dest);
void dt_print_node(const struct device_tree_node *node);
+size_t dt_read_reg_prop(struct device_tree_node *node, u32 addr_cells, u32 size_cells,
+ struct device_tree_region regions[], size_t regions_count);
/* Read #address-cells and #size-cells properties from a node. */
void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp,
u32 *sizecp);
--
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Ashish Kumar Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 18:
(1 comment)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/f6cce97c_63454f8b?us… :
PS8, Line 37: VTD_BASE_ADDRESS
> > VTD BAR and DMI3BAR are different BARs at different addresses. DMI3BAR NA for PTL mobile. […]
This indicates ADL and earlier, where this address was used for VTDBAR. In MTL-PTL it was updated as DMI3BAR. VTDBAR moved to a different address.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email )
Change subject: soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
......................................................................
soc/intel/mtl: Increase CAR_STACK_SIZE by 31KB for coreboot compatibility
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
TEST=None
Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83540
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
Dinesh Gehlot: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 612182b..ec8c318 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -171,12 +171,12 @@
config DCACHE_BSP_STACK_SIZE
hex
- default 0x80400
+ default 0x88000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
- (~1KiB).
+ (~32KiB).
config FSP_TEMP_RAM_SIZE
hex
--
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