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Change subject: mb/emulation/qemu-sbsa: Generate PPTT ACPI table
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/emulation/qemu-sbsa/pptt.c:
https://review.coreboot.org/c/coreboot/+/79108/comment/8e940443_c30aa789?us… :
PS7, Line 9: #define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type
: #define CLUSTER_FLAGS 0x11 // physical package, ID invalid, no thread, no leaf, identical impl.
: #define CORE_FLAGS 0x1a // no physical package, ID valid, no thread, leaf, identical impl.
:
: #define CACHE_ATTR_TYPE_DATA (0)
: #define CACHE_ATTR_TYPE_INSTRUCTION (0x1 << 2)
: #define CACHE_ATTR_TYPE_UNIFIED (0x1 << 3)
Would it make sense to have this in the header exposing acpi_get_pptt_topology?
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Hello Amanda Hwang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83657?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+2 by Amanda Hwang
Change subject: mb/google/brya/var/orisa: Update fw_config probe for storage devices
......................................................................
mb/google/brya/var/orisa: Update fw_config probe for storage devices
1. Add STORAGE_UNKNOWN fw_config to enable all storage devices.
2. Update fw_config probe to enable/disable devices in devicetree.
3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config
is enabled.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: Id3a22aa2206e86fdca6f6fadbc849572890fee58
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/mainboard/google/brya/variants/orisa/Makefile.mk
M src/mainboard/google/brya/variants/orisa/fw_config.c
M src/mainboard/google/brya/variants/orisa/overridetree.cb
D src/mainboard/google/brya/variants/orisa/variant.c
4 files changed, 25 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83657/4
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Change subject: mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10
......................................................................
mb/google/brya/var/trulo: Add USB2 Bluetooth device on Port 10
This change adds a new USB2 Bluetooth device configuration on Port 10
for the Trulo variant.
* A new `drivers/usb/acpi` chip is added with:
* `desc` set to "USB2 Bluetooth"
* `type` set to "UPC_TYPE_INTERNAL"
* `reset_gpio` set to "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
* `device` referencing `usb2_port10`
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I9a92a4d008eb4d0c339079ecbbb77facece435ba
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/83666/1
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index a9be57c..3ae9f85 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -446,6 +446,12 @@
device ref usb2_port5 on end
end
chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83663?usp=email )
Change subject: mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard
......................................................................
mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard
This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.
This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.
Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
CNVi WLAN has been removed.
This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/mainboard/google/brya/variants/orisa/overridetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/83663/1
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index 9e6378f..f048dbb 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -15,7 +15,8 @@
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
- register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
+ # USB 2.0 Port #10 must be used for integrated BT with Intel CNVi
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index f04eee2..9843272 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -90,7 +90,6 @@
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
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