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Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83331?usp=email )
Change subject: lib/smbios: Create SMBIOS type 4 entry
......................................................................
Patch Set 2:
(1 comment)
File src/lib/smbios.c:
https://review.coreboot.org/c/coreboot/+/83331/comment/deb1476c_28968d93?us… :
PS1, Line 446: nsigned int __weak smbios_get_max_socket(void)
: {
: return 1;
: }
> How about the following, without the weak function: […]
Done
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Hello Arthur Heymans, Jincheng Li, Lean Sheng Tan, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: lib/smbios: Create SMBIOS type 4 entry
......................................................................
lib/smbios: Create SMBIOS type 4 entry
One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.
TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos
Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/include/smbios.h
M src/lib/Kconfig
M src/lib/smbios.c
3 files changed, 19 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83331/2
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Hello Arthur Heymans, Jincheng Li, Lean Sheng Tan, Patrick Rudolph,
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Code-Review+2 by Arthur Heymans
Change subject: mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
mb/intel/avenuecity_crb: Update SMBIOS type 0,1,2,3 info
Update BIOS version and unset card bus plugin support.
Update wake-up type and SKU number.
Update mainboard asset tag and feature flags.
Update mainboard enclosure type, chassis version, chassis serial
number and chassis power cords.
Change-Id: I8e68c057fefa1d408fb8d69fef066cb573c929a4
Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com>
---
M src/mainboard/intel/avenuecity_crb/ramstage.c
1 file changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83328/2
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Hello Arthur Heymans, Jincheng Li, Lean Sheng Tan, Patrick Rudolph,
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Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
Update BIOS version and unset card bus plugin support.
Update wake-up type and SKU number.
Update mainboard asset tag and feature flags.
Update mainboard enclosure type, chassis version, chassis serial
number and chassis power cords.
Change-Id: I8a7d4958171df121e2cd3acb3a71554c695d64ab
Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com>
---
M src/mainboard/intel/beechnutcity_crb/Kconfig
M src/mainboard/intel/beechnutcity_crb/ramstage.c
2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83327/2
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos
TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20
Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/gnr/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
M src/soc/intel/xeon_sp/spr/romstage.c
5 files changed, 149 insertions(+), 170 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83325/2
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Change subject: mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
......................................................................
mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/mainboard/intel/frost_creek/Kconfig
A src/mainboard/intel/frost_creek/Kconfig.name
A src/mainboard/intel/frost_creek/Makefile.mk
A src/mainboard/intel/frost_creek/acpi/mainboard.asl
A src/mainboard/intel/frost_creek/acpi/platform.asl
A src/mainboard/intel/frost_creek/acpi_tables.c
A src/mainboard/intel/frost_creek/board.fmd
A src/mainboard/intel/frost_creek/board_id.c
A src/mainboard/intel/frost_creek/board_id.h
A src/mainboard/intel/frost_creek/board_info.txt
A src/mainboard/intel/frost_creek/devicetree.cb
A src/mainboard/intel/frost_creek/dsdt.asl
A src/mainboard/intel/frost_creek/gpio.inc
A src/mainboard/intel/frost_creek/ramstage.c
A src/mainboard/intel/frost_creek/ramstage.h
A src/mainboard/intel/frost_creek/romstage.c
A src/mainboard/intel/frost_creek/romstage.h
17 files changed, 660 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/4
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Change subject: soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/gpmr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
72 files changed, 5,865 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/4
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Change subject: soc/intel/common/block/imc: add Integrated Memory Controller driver
......................................................................
soc/intel/common/block/imc: add Integrated Memory Controller driver
This patch wraps the smbus IO calls with weak spd IO functions so that
firmware could use IMC to get SPD data.
Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/spd_bin.h
A src/soc/intel/common/block/imc/Kconfig
A src/soc/intel/common/block/imc/Makefile.mk
A src/soc/intel/common/block/imc/imc.c
A src/soc/intel/common/block/imc/spd.c
M src/soc/intel/common/block/include/intelblocks/imc.h
M src/soc/intel/common/block/smbus/smbuslib.c
M src/southbridge/intel/common/smbus.c
8 files changed, 293 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83320/3
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