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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
Bujia has 4 thermal sensors, so add the missing sensors settings.
Rename previous thermal sensors name to CPU and CPUVR.
BUG=b:327549688
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83302/4
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1:
(3 comments)
Patchset:
PS1:
> If gpio config is not correct, touchpad would never work. […]
Acknowledged
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/83346/comment/62b8d3f9_19c8f2b0?us… :
PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG),
> Actually this was the original config in baseboard/brya/gpio.c […]
Acknowledged
File src/mainboard/google/brya/variants/xol/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83346/comment/b2cd8c5e_d88812e8?us… :
PS1, Line 347: register "generic.detect" = "1"
> We had the issue with this original config.
Acknowledged
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1: -Code-Review
(1 comment)
Patchset:
PS1:
> Just found this CL that hasn't cherry-picked into firmware branch, let me check with this patch. […]
We are able to reproduce the issue with it. It seems we need this patch for now.
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1: Code-Review-1
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Just found this CL that hasn't cherry-picked into firmware branch, let me check with this patch.
https://review.coreboot.org/c/coreboot/+/72648
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1:
(3 comments)
Patchset:
PS1:
> IMO, the missing gpio. […]
If gpio config is not correct, touchpad would never work. The issue appeared after continuosly use of toupad.
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/83346/comment/83782472_d621e88d?us… :
PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG),
> PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
Actually this was the original config in baseboard/brya/gpio.c
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/src/…
File src/mainboard/google/brya/variants/xol/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83346/comment/027fba5f_0ce9762f?us… :
PS1, Line 347: register "generic.detect" = "1"
> register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" […]
We had the issue with this original config.
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 1:
(3 comments)
Patchset:
PS1:
IMO, the missing gpio.c entry is the reason behind this problem
File src/mainboard/google/brya/variants/xol/gpio.c:
https://review.coreboot.org/c/coreboot/+/83346/comment/c98796ce_ca1270f2?us… :
PS1, Line 123: PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG),
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
File src/mainboard/google/brya/variants/xol/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83346/comment/52c5619a_2b8cea9e?us… :
PS1, Line 347: register "generic.detect" = "1"
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "wake" = "GPE0_DW2_14"
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Verified-1 by build bot (Jenkins)
Change subject: lib/smbios: Create SMBIOS type 4 entry
......................................................................
lib/smbios: Create SMBIOS type 4 entry
One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.
TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos
Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/include/smbios.h
M src/lib/Kconfig
M src/lib/smbios.c
M src/soc/intel/xeon_sp/util.c
4 files changed, 24 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83331/3
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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos
TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20
Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/gnr/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
M src/soc/intel/xeon_sp/spr/romstage.c
5 files changed, 153 insertions(+), 170 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83325/3
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yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email )
Change subject: soc/intel/common/systemagent: improve systemagent
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Patch Set 3:
(6 comments)
File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/83318/comment/ceed31e9_c688ac38?us… :
PS3, Line 78: return;
> If no HAVE_CAPID_A_REGISTER, all remaining logics will not run?
Yes because the remaining logics are all depends on the value of CAPID_A register.
https://review.coreboot.org/c/coreboot/+/83318/comment/3481692d_43a4f116?us… :
PS3, Line 133: .is_limit = CONFIG(TOUUD_LIMIT),
> Is there any HW hints could be used to decide is_limit? or we have to use a SoC specific Kconfig to […]
I think there is no hints, it's specified in EDS. On most client platforms, the lower bits should be treated as 0s, so we can set the default Kconfig value to "n" and overwrite it to "y" on specific platform.
https://review.coreboot.org/c/coreboot/+/83318/comment/932164df_261d4e15?us… :
PS3, Line 176: value = ALIGN_DOWN(value + entry->align, entry->align);
> this is to align up?
The lower bits of the registers are read as 0s but should be treated as 1s, thus aligning up works.
File src/soc/intel/common/block/systemagent/systemagent_def.h:
https://review.coreboot.org/c/coreboot/+/83318/comment/f93d0b36_08faea0b?us… :
PS3, Line 73: * IS_LIMIT = If registers/offset indicates address limit or address limit plus 1.
> Not sure if the handling of IS_LIMIT is a common case? Or explicitly explain how will be processed o […]
IS_LIMIT indicates whether the lower bits should be treated as 1s or 0s, although they are read as 0s. I think I should give more comments here.
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/83318/comment/a0be6529_b10dada5?us… :
PS3, Line 133: uint32_t tolud = pci_read_config32(SA_DEV_ROOT, TOLUD);
> Is there any possibility to load from sa_read_map_entry instead of re-read from PCI config space her […]
If calling sa_read_map_entry(), we should pass a device to it, but this function may be called before device tree is available (e.g., in romstage).
https://review.coreboot.org/c/coreboot/+/83318/comment/75cb19e6_a20001de?us… :
PS3, Line 161: return ALIGN_DOWN((pci_read_config32(SA_DEV_ROOT, TSEG + 4) +
> It looks like TSEG + 4 will return a CONFIG_TSEG_ALIGNMENT aligned limit value, but we need to pci_r […]
Yes because the lower bits are read as 0s but should be treated as 1s.
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