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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/brya/variants/bujia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83302/comment/4a98454d_010b999c?us… :
PS4, Line 86: CHARGER
> Any reason for removing Charger control (throttling input charging current) in new code change?
modify done. thanks
https://review.coreboot.org/c/coreboot/+/83302/comment/99b906d7_d0afdeac?us… :
PS4, Line 66: CPU
> Any reason for changing the sensor0 name from DRAM to CPU? We have DPTF_CPU available and used in ac […]
got it, i modify to that add new two tsr
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Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
Bujia has 4 thermal sensors, so add two missing sensors settings.
BUG=b:327549688
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83302/8
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
Bujia has 4 thermal sensors, so add two missing sensors settings.
BUG=b:327549688
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
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---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83302/7
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Change subject: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/power_limit.h:
https://review.coreboot.org/c/coreboot/+/69217/comment/18dff202_192213d1?us… :
PS3, Line 16: MOBILE_SKU_PL1_TIME_SEC
It might make sense for me to change this macro name as well which reflects the Time in Seconds, something like this "POWER_LIMIT1_TIME_28_SEC"
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Change subject: cpu/x86/smm: Add save state ops for different save states
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/amd/smm/amd64_save_state.c:
https://review.coreboot.org/c/coreboot/+/83064/comment/f77694e3_64bb3685?us… :
PS4, Line 117: 0x00020064
This one doesn't have I/O Instruction Restart bit set, which in turn means that `smm_io_trap` in `amd64_apmc_node()` won't have useful data. It is used by QEMU, which is the sole reason why I couldn't use changes from this chain in CB:82558.
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Change subject: mb/google/brox/var/lotso: Update DTT settings for thermal control
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83304/comment/48472bb5_17ef1232?us… :
PS3, Line 9: 348285763
Add me in this bug to understand the current changes. Thanks.
File src/mainboard/google/brox/variants/lotso/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83304/comment/8d0604a4_9bbf2792?us… :
PS3, Line 126: 12000
Please share the reason for changing this to lower value, ie. from 15W to 12W.
https://review.coreboot.org/c/coreboot/+/83304/comment/4a11b495_dd519962?us… :
PS3, Line 134: 25000
Share details on lowering the PL2 Max and Min values from 55W to 25W.
Did you get chance to check the Benchmark/system performance with this change?
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Change subject: util/ifdtool: dump SPI modes from FLCOMP
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83282/comment/9b324f51_361a9517?us… :
PS1, Line 9: These fields are documented in the Alder Lake-S Client Platform SPI
: Programming Guide, but they are not presented in the Skylake-LP
: Client Platform SPI Programming Guide
> It would be nice if someone who has access to Coffee Lake SPI guide could confirm that these fields […]
It's not really a concern. So mark it as resolved
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83302/comment/93074cd5_ba56cbda?us… :
PS4, Line 12: 327549688
Please add me in the bug to go through the history on this. Thanks.
File src/mainboard/google/brya/variants/bujia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83302/comment/6d76ff4c_580ce1aa?us… :
PS4, Line 86: CHARGER
Any reason for removing Charger control (throttling input charging current) in new code change?
https://review.coreboot.org/c/coreboot/+/83302/comment/7e03ee7b_b18ca870?us… :
PS4, Line 66: CPU
Any reason for changing the sensor0 name from DRAM to CPU? We have DPTF_CPU available and used in active policy below at line #75.
Also, same question for sensor1 name change.
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