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Change subject: driver/intel/fsp2_0: Prevent error logs during S3 wakeup
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/intel/fsp2_0/fsp_gop_blt.c:
https://review.coreboot.org/c/coreboot/+/83055/comment/354f6c00_18d20c01?us… :
PS2, Line 245: /* CBMEM is locked for S3 resume path. */
: if (acpi_is_wakeup_s3())
: return;
> I can investigate further, but the bmp_load_logo() function in lib/bmp_logo. […]
Can we resolve this for the error msg in S3 cycle ? And plan to include FW splash screen while resuming S3 if needed.
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Change subject: Make Ada a first class citizen
......................................................................
Patch Set 16:
(1 comment)
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/13044/comment/a3fa12fc_729cad7b?us… :
PS16, Line 362: +=
isn't `ADAFLAGS_common := -gnatg -gnatp`?
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Change subject: brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
See if we can trigger the merge
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Change subject: soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
......................................................................
soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/3
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FsptUpd.h
4 files changed, 1,391 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83192/4
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Change subject: vc/intel/fsp/snr: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Keep this open.
I don't have the specific FSP commit version because I used the one in the binaries release. It is downloaded from RDC, and I'm not sure if extra permission is required to download it.
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Change subject: brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
......................................................................
brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable
the MPHY clock in the SKU2 configuration to ensure that S0ix functions
normally.
BUG=b:350609955
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450
Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/83323/2
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