coreboot-gerrit July 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: allow soc to have specific gpmr definition
by Shuo Liu (Code Review) 04 Jul '24

04 Jul '24

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[L] Change in coreboot[main]: soc/intel/common/block/imc: add Integrated Memory Controller driver
by Shuo Liu (Code Review) 04 Jul '24

04 Jul '24

Attention is currently required from: yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: add Integrated Memory Controller driver ...................................................................... Patch Set 3: (4 comments) File src/soc/intel/common/block/imc/Kconfig: https://review.coreboot.org/c/coreboot/+/83320/comment/97eda60a_99d6dc77?us… : PS3, Line 4: bool I guess you are using an IMC with an SMBUS in it? Would it be possible to be more explicit on naming? File src/soc/intel/common/block/imc/imc.c: https://review.coreboot.org/c/coreboot/+/83320/comment/51982270_8abfef5d?us… : PS3, Line 57: void imc_smbus_spd_init(pci_devfn_t dev) imc_spd_smbus_init? File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/d3de02c6_6ee8b429?us… : PS3, Line 10: { Can we not using weak since it would be confusing? IMO, there are 2 implementation, one is the default, one is the IMC SMBUS based. https://review.coreboot.org/c/coreboot/+/83320/comment/7844c74e_f0c9e8e6?us… : PS3, Line 96: if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) && blk->addr_map[i] == 0) { I guess SOC_INTEL_COMMON_BLOCK_IMC will provide SPD data not depending on blk->addr_map[i]? -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Thu, 04 Jul 2024 03:13:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/common/systemagent: improve systemagent
by Shuo Liu (Code Review) 04 Jul '24

04 Jul '24

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[M] Change in coreboot[main]: soc/intel/common/systemagent: improve systemagent
by Shuo Liu (Code Review) 04 Jul '24

04 Jul '24

Attention is currently required from: Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: improve systemagent ...................................................................... Patch Set 3: (8 comments) File src/soc/intel/common/block/systemagent/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/c887d602_edc7d2b2?us… : PS3, Line 68: treated as 1s. Seem not quite clear, do you have example for this? File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/83318/comment/f932ed0e_1e664562?us… : PS3, Line 78: return; If no HAVE_CAPID_A_REGISTER, all remaining logics will not run? https://review.coreboot.org/c/coreboot/+/83318/comment/51566f97_67678eba?us… : PS3, Line 133: .is_limit = CONFIG(TOUUD_LIMIT), Is there any HW hints could be used to decide is_limit? or we have to use a SoC specific Kconfig to specify? https://review.coreboot.org/c/coreboot/+/83318/comment/cbcdb77f_48d5afc2?us… : PS3, Line 176: value = ALIGN_DOWN(value + entry->align, entry->align); this is to align up? https://review.coreboot.org/c/coreboot/+/83318/comment/8866af84_78efdec4?us… : PS3, Line 307: if (CONFIG(HAVE_MULTIPLE_DOMAINS) && dev->upstream->secondary != 0) I guess even no HAVE_MULTIPLE_DOMAINS, if (dev->upstream->secondary != 0) also work. But this is for safe. File src/soc/intel/common/block/systemagent/systemagent_def.h: https://review.coreboot.org/c/coreboot/+/83318/comment/6cbb6b05_beb7f3b4?us… : PS3, Line 73: * IS_LIMIT = If registers/offset indicates address limit or address limit plus 1. Not sure if the handling of IS_LIMIT is a common case? Or explicitly explain how will be processed on values with IS_LIMIT here (e.g. to align up)? File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/83318/comment/69af878b_0daa62b8?us… : PS3, Line 133: uint32_t tolud = pci_read_config32(SA_DEV_ROOT, TOLUD); Is there any possibility to load from sa_read_map_entry instead of re-read from PCI config space here? https://review.coreboot.org/c/coreboot/+/83318/comment/0ddea97d_2f897e16?us… : PS3, Line 161: return ALIGN_DOWN((pci_read_config32(SA_DEV_ROOT, TSEG + 4) + It looks like TSEG + 4 will return a CONFIG_TSEG_ALIGNMENT aligned limit value, but we need to pci_read_config32(SA_DEV_ROOT, TSEG + 4) | (CONFIG_TSEG_ALIGNMENT - 1) to make it fully active? -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jul 2024 02:49:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
by SH Kim (Code Review) 04 Jul '24

04 Jul '24

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email ) Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT ...................................................................... mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT If user continues to use the touchpad for over 3 minutes on Xol, the pointer movement is stuttering. Touchpad I2C transaction should appear during the interrupt signal level is low, but we could see some more I2C transaction after the interrupt signal(GPP_F14) went to high. We found experimentally that changing the interrupt type to GPIO_INT from APIC_IRQ improved this issue. We are still investigating, would like to apply this change first for Xol's dogfooding. BUG=b:350609957 BRANCH=brya TEST=built and verified there's no stuttering issue on touchpad movement Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xol/gpio.c M src/mainboard/google/brya/variants/xol/overridetree.cb 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83346/1 diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 39478a1..fea66e4 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -119,6 +119,8 @@ PAD_NC(GPP_F12, NONE), /* F13 : GSXDOUT ==> NC */ PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ + PAD_CFG_GPI_INT_LOCK(GPP_F14, NONE, LEVEL, LOCK_CONFIG), /* F15 : GSXSRESET# ==> PU 100K 3.3V */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* F16 : GSXCLK ==> NC */ diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index d73702c..945b8b8 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -343,8 +343,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ZNT0000"" register "generic.desc" = ""Zinitix Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "generic.wake" = "GPE0_DW2_14" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F14)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0xE" device i2c 40 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/83346?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c Gerrit-Change-Number: 83346 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: allow soc to have specific gpmr definition
by Name of user not set (Code Review) 04 Jul '24

04 Jul '24

Attention is currently required from: Jérémy Compostella, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83317?usp=email ) Change subject: soc/intel/common/block/gpmr: allow soc to have specific gpmr definition ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/include/intelblocks/gpmr.h: https://review.coreboot.org/c/coreboot/+/83317/comment/2bec869d_126e9dfe?us… : PS3, Line 10: #include <soc/gpmr.h> > Is these GPMR as additional sets based on ioc_gpmr or pcr_gpmr? […] There is no IOC support in this platform, thus it's only based on pcr_gpmr. By the way from IOC definition, it's used when there is no PCH die. -- To view, visit https://review.coreboot.org/c/coreboot/+/83317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94797a72af75fc96ab2cacb1d46b581605a15387 Gerrit-Change-Number: 83317 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jul 2024 02:31:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
by Eric Lai (Code Review) 04 Jul '24

04 Jul '24

Attention is currently required from: Karthik Ramasubramanian, Kun Liu, Subrata Banik, Wentao Qin. Eric Lai has posted comments on this change by Wentao Qin. ( https://review.coreboot.org/c/coreboot/+/83323?usp=email ) Change subject: mb/google/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83323/comment/a638522b_54daaea3?us… : PS1, Line 7: lotso brox/var/lotso: -- To view, visit https://review.coreboot.org/c/coreboot/+/83323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450 Gerrit-Change-Number: 83323 Gerrit-PatchSet: 1 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Jul 2024 02:25:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya: Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURAT...
by Eric Lai (Code Review) 04 Jul '24

04 Jul '24

Attention is currently required from: Amanda Hwang, Kapil Porwal, Nick Vaccaro. Eric Lai has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/83324?usp=email ) Change subject: mb/google/brya: Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION for orisa ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83324?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f740bedc8ff667d15f077fa57d201ab0d42ebf8 Gerrit-Change-Number: 83324 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Jul 2024 02:24:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: allow soc to have specific gpmr definition
by Shuo Liu (Code Review) 04 Jul '24

04 Jul '24

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[XS] Change in coreboot[main]: mb/google/brya: disable early EC sync for orisa
by Eric Lai (Code Review) 04 Jul '24

04 Jul '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83303?usp=email ) Change subject: mb/google/brya: disable early EC sync for orisa ...................................................................... mb/google/brya: disable early EC sync for orisa Disable VBOOT_EARLY_EC_SYNC for all trulo boards. BUG=b:345112878 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 59b09e0..4f4045a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -856,7 +856,7 @@ default "pujjoga" if BOARD_GOOGLE_PUJJOGA config VBOOT - select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA + select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) select VBOOT_LID_SWITCH config UART_FOR_CONSOLE -- To view, visit https://review.coreboot.org/c/coreboot/+/83303?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a Gerrit-Change-Number: 83303 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2024