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Change subject: mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/intel/frost_creek/COPYING-NOTICE:
PS3:
> This probably doesn't belong here.
Ok, I've removed it.
File src/mainboard/intel/frost_creek/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/83322/comment/a249a49e_b947f385?us… :
PS3, Line 22: Store (Arg0, SMIF) // SMI Function
: Store (0,
> Please use ASL2 syntax
Ok, I've updated all asl files to follow ASL2 syntax.
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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
......................................................................
Patch Set 2:
(1 comment)
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/83314/comment/a1143fc3_e91f140b?us… :
PS1, Line 86: #define CPUID_SNOWRIDGE_A0 0x80660
> Isn't it missing an extra tab for indentation ?
Yes, I've added it.
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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/711a0d21_4ab955be?us… :
PS2, Line 8:
> oops, please follow Felix's comment, but capitalize the 1st letter (add -> Add)
Should the first letter in the commit summary be capitalized? If so, I need to update all the commits.
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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/a8c58869_a081f7f2?us… :
PS2, Line 8:
> Add CPU and PCIe definitions for SNR
oops, please follow Felix's comment, but capitalize the 1st letter (add -> Add)
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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
......................................................................
Patch Set 2:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/83314/comment/5b4e16b3_1b11f05b?us… :
PS2, Line 8:
Add CPU and PCIe definitions for SNR
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