Attention is currently required from: Julius Werner, Paul Menzel, Shelley Chen.
Bharath N has posted comments on this change by Bharath N. ( https://review.coreboot.org/c/qc_blobs/+/83305?usp=email )
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/qc_blobs/+/83305/comment/320e6505_a049d819?us… :
PS1, Line 8: TEST=Validated on qualcomm sc7180 development board
> Please add a blank line above.
Done
--
To view, visit https://review.coreboot.org/c/qc_blobs/+/83305?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: qc_blobs
Gerrit-Branch: main
Gerrit-Change-Id: Ia390035cdd591c1d31fd2e28ad53e63d16e91a37
Gerrit-Change-Number: 83305
Gerrit-PatchSet: 2
Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com>
Gerrit-Attention: Shelley Chen <shchen(a)google.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:40:29 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Attention is currently required from: Michał Żygowski, Subrata Banik, Tarun Tuli.
Paul Menzel has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/69217?usp=email )
Change subject: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69217/comment/ac3a0840_33a1eef7?us… :
PS3, Line 16:
Tested how?
--
To view, visit https://review.coreboot.org/c/coreboot/+/69217?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I02c56b981d956bef58ae90f7f317a231416a2e54
Gerrit-Change-Number: 69217
Gerrit-PatchSet: 3
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com>
Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:40:23 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Attention is currently required from: Bharath N, Julius Werner, Shelley Chen.
Hello Julius Werner, Shelley Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/qc_blobs/+/83305?usp=email
to look at the new patch set (#2).
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ia390035cdd591c1d31fd2e28ad53e63d16e91a37
Signed-off-by: Bharath N <quic_bharn(a)quicinc.com>
---
M sc7180/qtiseclib/Release_Notes.txt
M sc7180/qtiseclib/libqtisec.a
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/05/83305/2
--
To view, visit https://review.coreboot.org/c/qc_blobs/+/83305?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: qc_blobs
Gerrit-Branch: main
Gerrit-Change-Id: Ia390035cdd591c1d31fd2e28ad53e63d16e91a37
Gerrit-Change-Number: 83305
Gerrit-PatchSet: 2
Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com>
Gerrit-Attention: Shelley Chen <shchen(a)google.com>
Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>
Gerrit-Attention: Bharath N <quic_bharn(a)quicinc.com>
Bharath N has abandoned this change. ( https://review.coreboot.org/c/qc_blobs/+/83348?usp=email )
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
Abandoned
wrong mail id
--
To view, visit https://review.coreboot.org/c/qc_blobs/+/83348?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: abandon
Gerrit-Project: qc_blobs
Gerrit-Branch: main
Gerrit-Change-Id: I5eaac050198effac681d3f87cb868ad92eebe622
Gerrit-Change-Number: 83348
Gerrit-PatchSet: 1
Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com>
Attention is currently required from: Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com.
Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email )
Change subject: soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/da3724d3_bc8a2dd7?us… :
PS3, Line 8:
Please add the source for these ids, like datasheet name, revision.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83314?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Gerrit-Change-Number: 83314
Gerrit-PatchSet: 3
Gerrit-Owner: yuchi.chen(a)intel.com
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: جوكر الطويل <goker.g700(a)gmail.com>
Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Attention: yuchi.chen(a)intel.com
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:38:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Attention is currently required from: Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com.
Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/c52920c1_3f887865?us… :
PS4, Line 100: This structure holds the DLL configuration
: register values that will be programmed by RC.
: Those policies should be used by platform if default values
: provided by RC are not sufficient to provide stable operation
: at all supported speed modes. RC will blindly set the DLL values
: as provided in this structure.
Line breaks make it harder to read.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83192?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Gerrit-Change-Number: 83192
Gerrit-PatchSet: 4
Gerrit-Owner: yuchi.chen(a)intel.com
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: yuchi.chen(a)intel.com
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:36:59 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com.
Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/a64c824b_66b3bbbf?us… :
PS4, Line 29: This file is automatically generated. Please do NOT modify !!!
Please add to the commit message, how it was generated.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83192?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Gerrit-Change-Number: 83192
Gerrit-PatchSet: 4
Gerrit-Owner: yuchi.chen(a)intel.com
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: yuchi.chen(a)intel.com
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:35:41 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com.
Paul Menzel has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/e8c0b16f_c4081f84?us… :
PS4, Line 3: Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Is that up to date?
--
To view, visit https://review.coreboot.org/c/coreboot/+/83192?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Gerrit-Change-Number: 83192
Gerrit-PatchSet: 4
Gerrit-Owner: yuchi.chen(a)intel.com
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: yuchi.chen(a)intel.com
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Comment-Date: Thu, 04 Jul 2024 12:34:30 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Bharath N has uploaded this change for review. ( https://review.coreboot.org/c/qc_blobs/+/83348?usp=email )
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
TEST=Validated on qualcomm sc7180 development board
Change-Id: I5eaac050198effac681d3f87cb868ad92eebe622
Signed-off-by: Bharath N <bharn(a)qualcomm.corp-partner.google.com>
---
M sc7180/qtiseclib/Release_Notes.txt
M sc7180/qtiseclib/libqtisec.a
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/48/83348/1
diff --git a/sc7180/qtiseclib/Release_Notes.txt b/sc7180/qtiseclib/Release_Notes.txt
index 018797c..f10e15d 100644
--- a/sc7180/qtiseclib/Release_Notes.txt
+++ b/sc7180/qtiseclib/Release_Notes.txt
@@ -1,4 +1,21 @@
-=================== Release 00050 ================================
+=================== Release 00071 ================================
+This Release Notes file covers these blobs:
+ * libqtisec.a
+
+Version : 00071
+
+Release Date : June 26, 2024
+
+Supported Silicon : SC7180
+
+Changes since last version :
+ * Support for ACR and NSACR in SMMU
+
+No special instructions, requirements or dependencies, files must be
+present in this folder to be pulled in during coreboot build
+
+Errata : Nothing to report
+=================== Release 00069 ================================
This Release Notes file covers these blobs:
* libqtisec.a
diff --git a/sc7180/qtiseclib/libqtisec.a b/sc7180/qtiseclib/libqtisec.a
index 2ab2c7b..8751fbd 100644
--- a/sc7180/qtiseclib/libqtisec.a
+++ b/sc7180/qtiseclib/libqtisec.a
Binary files differ
--
To view, visit https://review.coreboot.org/c/qc_blobs/+/83348?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: qc_blobs
Gerrit-Branch: main
Gerrit-Change-Id: I5eaac050198effac681d3f87cb868ad92eebe622
Gerrit-Change-Number: 83348
Gerrit-PatchSet: 1
Gerrit-Owner: Bharath N <quic_bharn(a)quicinc.com>