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Change subject: xcompile: Add -Wextra with temporary exceptions
......................................................................
Set Ready For Review
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Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/80501?usp=email )
Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
......................................................................
Patch Set 8:
(13 comments)
File src/mainboard/protectli/vault_adl_p/Kconfig:
https://review.coreboot.org/c/coreboot/+/80501/comment/dc5c9f40_04af61bb?us… :
PS7, Line 38: default 0
> Isn't this the global default anyway?
Yes, no idea what it is doing here. Removed
File src/mainboard/protectli/vault_adl_p/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/bd6713cc_32ec8958?us… :
PS7, Line 41: polarity << pin
> I will look into ITE datasheets I have at hand and see how much can be shared. […]
Prepared a patch with a generic ITE SIo GPIO driver: CB:83355
File src/mainboard/protectli/vault_adl_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80501/comment/1be68e07_38f419a9?us… :
PS7, Line 20: device cpu_cluster 0 on end
> Equal to chipset devicetree, please remove
Done
https://review.coreboot.org/c/coreboot/+/80501/comment/f7ae0b9e_2099b687?us… :
PS7, Line 46: register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # 5G module
: register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB2.0 + USB 3.0 column with RJ45
: register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB Type-C no TBT
:
> ```suggestion […]
Done
https://review.coreboot.org/c/coreboot/+/80501/comment/3f7a463e_71abb6fa?us… :
PS7, Line 93: register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB1
: register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 USB1
: register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # 5G
: register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 internal
: register "usb2_ports[4]" = "USB2_PORT_EMPTY"
: register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2
: register "usb2_ports[6]" = "USB2_PORT_EMPTY"
: register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C no TBT
: register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2
:
> Removes ports 4 and 6 too. […]
Done
https://review.coreboot.org/c/coreboot/+/80501/comment/2a88d5b9_33be2ebd?us… :
PS7, Line 103: register "usb2_ports[10]" = "USB2_PORT_EMPTY"
: register "usb2_ports[11]" = "USB2_PORT_EMPTY"
: register "usb2_ports[12]" = "USB2_PORT_EMPTY"
: register "usb2_ports[13]" = "USB2_PORT_EMPTY"
: register "usb2_ports[14]" = "USB2_PORT_EMPTY"
: register "usb2_ports[15]" = "USB2_PORT_EMPTY"
:
: register "usb3_ports[0]" = "USB3_PORT_EMPTY"
: register "usb3_ports[1]" = "USB3_PORT_EMPTY"
: register "usb3_ports[2]" = "USB3_PORT_EMPTY"
: register "usb3_ports[3]" = "USB3_PORT_EMPTY"
: register "usb3_ports[4]" = "USB3_PORT_EMPTY"
: register "usb3_ports[5]" = "USB3_PORT_EMPTY"
: register "usb3_ports[6]" = "USB3_PORT_EMPTY"
: register "usb3_ports[7]" = "USB3_PORT_EMPTY"
: register "usb3_ports[8]" = "USB3_PORT_EMPTY"
: register "usb3_ports[9]" = "USB3_PORT_EMPTY"
> It does, yes. Please remove. […]
Done
https://review.coreboot.org/c/coreboot/+/80501/comment/b13c1b49_2cb06263?us… :
PS7, Line 193: device ref heci1 on end
> Equal to chipset devicetree, please remove.
Done
https://review.coreboot.org/c/coreboot/+/80501/comment/df78af6f_af331a6b?us… :
PS7, Line 206: PCIE_RP_CLK_SRC_UNUSED
> Given that you enable one clock per port, it doesn't seem unused. Or […]
I have added the appropriate CLK_SRC pins.
https://review.coreboot.org/c/coreboot/+/80501/comment/8daac9dd_23a523cd?us… :
PS7, Line 317: end
> This got me curious. […]
Usually the PC80 TPM was on LPC bus. ESPI is an LPC successor, so I leave the TPM there. We may move it under SPI device, but then the hierarchy in ACPI will cause the TPM to depend on the SPI device 1f.5. Typically the TPM device should live under \_SB directly, so I wonder where it should really be placed.
https://review.coreboot.org/c/coreboot/+/80501/comment/b6e90c5f_2397cd8f?us… :
PS7, Line 320: device ref p2sb hidden end
> Equal to chipset devicetree, please remove.
Done
File src/mainboard/protectli/vault_adl_p/gpio.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/b80f7616_dcaca785?us… :
PS7, Line 16: static const struct pad_config gpio_table[] = {
> Remove comments for pads not connected.
Done
File src/mainboard/protectli/vault_adl_p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/ac1aac6b_cc3fef05?us… :
PS7, Line 29: }
> Déjà vu. Shouldn't this be shared with `die. […]
Exported it to a header file as static inline function
https://review.coreboot.org/c/coreboot/+/80501/comment/438f898b_f9f617e0?us… :
PS7, Line 51: }
> Another déjà vu. Please share code where possible. For instance, this could […]
Haven't touched it yet. Will update it soon with another patch.
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83356?usp=email )
Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
......................................................................
soc/intel/alderlake/tcss: Add definition of IOM_READY bit
Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1
register. Needed by Protectli VP66XX boards to poll for this bit
before FSP Silicon Init to have USB functionality.
TEST=Poll the IOM_READY bit on VP66XX platform and observe the
TCSS XHCI is up in lspci.
Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/soc/intel/alderlake/include/soc/tcss.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83356/1
diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h
index 014e307..825b6c7 100644
--- a/src/soc/intel/alderlake/include/soc/tcss.h
+++ b/src/soc/intel/alderlake/include/soc/tcss.h
@@ -7,6 +7,10 @@
#define IOM_CSME_IMR_TBT_STATUS 0x14
#define TBT_VALID_AUTHENTICATION (1 << 30)
+/* TCSS IP status */
+#define IOM_TYPEC_STATUS_1 0x50
+#define IOM_READY (1 << 30)
+
/* IOM aux bias control registers in REGBAR MMIO space */
#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070
#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
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Hello Nico Huber, Piotr Król, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80501?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
......................................................................
mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
It is a new incoming Protectli product based on Alder Lake-P SoC.
More details and documentation will be added later.
TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670.
Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
A src/mainboard/protectli/vault_adl_p/Kconfig
A src/mainboard/protectli/vault_adl_p/Kconfig.name
A src/mainboard/protectli/vault_adl_p/Makefile.mk
A src/mainboard/protectli/vault_adl_p/acpi/superio.asl
A src/mainboard/protectli/vault_adl_p/board_beep.h
A src/mainboard/protectli/vault_adl_p/board_info.txt
A src/mainboard/protectli/vault_adl_p/bootblock.c
A src/mainboard/protectli/vault_adl_p/data.vbt
A src/mainboard/protectli/vault_adl_p/devicetree.cb
A src/mainboard/protectli/vault_adl_p/die.c
A src/mainboard/protectli/vault_adl_p/dsdt.asl
A src/mainboard/protectli/vault_adl_p/gpio.c
A src/mainboard/protectli/vault_adl_p/gpio.h
A src/mainboard/protectli/vault_adl_p/hda_verb.c
A src/mainboard/protectli/vault_adl_p/mainboard.c
A src/mainboard/protectli/vault_adl_p/romstage_fsp_params.c
A src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd
17 files changed, 1,278 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/80501/8
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Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
As mentioned last time during review that there has to be a board backed up by new SoC development. (as coreboot builder won't be able to build PTL SoC w/o an underlying board)
ideally we should have used fatcat to select PTL Kconfig to start the build. This will also help us to catch the compilation issue.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:329787286
TEST=verified on Panther Lake Simics PSS.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pch.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
13 files changed, 1,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/2
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