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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:329787286
TEST=verified on Panther Lake Simics PSS.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pch.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
13 files changed, 1,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/3
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Change subject: mb/google/trulo/var/orisa: Add fw_config field for PDC control
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
If use in OS level, coreboot no need to add, but fine.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
......................................................................
mb/google/brox/var/lotso: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable
the MPHY clock in the SKU2 configuration to ensure that S0ix functions
normally.
BUG=b:350609955
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450
Signed-off-by: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/83323/3
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Change subject: mb/google/trulo/var/orisa: Add fw_config field for PDC control
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> where and when will this be used?
This will be used for PDC (Realtek/TI) FW AU.
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Change subject: mb/google/brox/var/lotso: Update DTT settings for thermal control
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83304/comment/2425448e_98176e03?us… :
PS3, Line 9: 348285763
> Add me in this bug to understand the current changes. Thanks.
Done
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