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Change subject: mb/google/brox/var/lotso: Update DTT settings for thermal control
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Patch Set 3: Code-Review+2
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Change subject: xcompile: Add -Wextra with temporary exceptions
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Patch Set 3:
(1 comment)
Patchset:
PS3:
I would have done the opposite.
"Wextra" may evolve with new options which may generate compilation errors in the future.
On the other hand, activating the options individually seems more appropriate to me.
Once you have covered all of the "Wextra" options, you can activate it.
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Change subject: mb/google/brox/var/lotso: Update DTT settings for thermal control
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
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Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83302/comment/ec1b0705_87db5768?us… :
PS8, Line 13: TEST= USE="-project_all project_bujia" emerge-brask coreboot
> We check form ACPI SSDT table on DUT. […]
It’d be nice, if you added that to the TEST= line in the commit message. Maybe even the commands and structure of the SSDT.
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/intel/mtlrvp: Set cnvi_wifi bluetooth companion device
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83310/comment/238c9709_283f6f7a?us… :
PS2, Line 7: Set cnvi_wifi bluetooth companion device
Maybe:
> Set USB2 port 10 as cnvi_wifi bluetooth companion device
https://review.coreboot.org/c/coreboot/+/83310/comment/dc05e29b_640ddda6?us… :
PS2, Line 14: return
return*s*?
File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83310/comment/d5c5318d_3f9683d4?us… :
PS2, Line 406: register "type" = "UPC_TYPE_INTERNAL"
Could be also mentioned in the commit message. Feel free to ignore though.
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
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Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83302/comment/e20f20f1_01ef7bb3?us… :
PS4, Line 12: 327549688
> Please add me in the bug to go through the history on this. Thanks.
I can access this bug now. It seems this bug is for tracking overall Bujia project.
If possible, can you please create a separate bug to discuss only these new thermal settings change so it will be useful for tracking purpose. Thanks.
Overall the changes looks good to me now.
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Change subject: mb/google/trulo/var/orisa: Add fw_config field for PDC control
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Patch Set 5:
(1 comment)
Patchset:
PS5:
> If use in OS level, coreboot no need to add, but fine.
This change is necessary because the FW AU framework will be implemented in depthcharge.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 3:
(1 comment)
Patchset:
PS2:
> As mentioned last time during review that there has to be a board backed up by new SoC development. […]
Hi Subrata, sure, valid point. Let me use the fatcat mainboard to build with PTL SoC.
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