Attention is currently required from: Abhishek Pandit-Subedi, Shelley Chen.
Keith Short has uploaded a new patch set (#2) to the change originally created by Abhishek Pandit-Subedi. ( https://review.coreboot.org/c/coreboot/+/83252?usp=email )
Change subject: ec/google/chromeec: Stop checking CBI for UCSI
......................................................................
ec/google/chromeec: Stop checking CBI for UCSI
The ucsi_enabled flag is no longer used by the EC. Update coreboot to only use only EC_FEATURE_UCSI_PPM to determine whether UCSI is enabled.
BUG=b:319124515
TEST=emerge-brox coreboot chromeos-bootimage
Cq-Depend: chromium:5664227
Change-Id: Ia9d820c637e56a527fd90f45b1848158a960dee7
Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org>
---
M src/ec/google/chromeec/ec.c
1 file changed, 1 insertion(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83252/2
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Gerrit-Change-Number: 83252
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Gerrit-Owner: Abhishek Pandit-Subedi <abhishekpandit(a)chromium.org>
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83343?usp=email )
Change subject: soc/amd/common/acpi/ivrs: use PCI_DEVFN macro
......................................................................
soc/amd/common/acpi/ivrs: use PCI_DEVFN macro
Use the PCI_DEVFN macro to make the calculation of the ivhd->device_id
value a bit clearer.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0
---
M src/soc/amd/common/block/acpi/ivrs.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/83343/1
diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c
index a2f7715..451a6c0 100644
--- a/src/soc/amd/common/block/acpi/ivrs.c
+++ b/src/soc/amd/common/block/acpi/ivrs.c
@@ -332,7 +332,7 @@
ivhd->length = sizeof(struct acpi_ivrs_ivhd);
/* BDF <bus>:00.2 */
- ivhd->device_id = 0x02 | (nb_dev->upstream->secondary << 8);
+ ivhd->device_id = PCI_DEVFN(0, 2) | (nb_dev->upstream->secondary << 8);
ivhd->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID);
ivhd->iommu_base_low = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_LO) & 0xffffc000;
ivhd->iommu_base_high = pci_read_config32(iommu_dev, IOMMU_CAP_BASE_HI);
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Gerrit-Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email )
Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
......................................................................
Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc.
Reason for revert: The version downloaded does not match the version
that is printed out when executing `iasl --version`. coreboot notices
that and refuses to compile QEMU-Q35 mainboard. I tested it on 2
different PCs.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83296
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/acpica-unix-20230628_iasl.patch
A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
D util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
4 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Felix Singer: Looks good to me, approved
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index f4379ad..ad75665 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -40,7 +40,7 @@
MPC_VERSION=1.3.1
GCC_VERSION=14.1.0
BINUTILS_VERSION=2.42
-IASL_VERSION=20240321
+IASL_VERSION="20230628"
# CLANG version number
CLANG_VERSION=18.1.6
CMAKE_VERSION=3.29.3
@@ -74,7 +74,7 @@
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/819451"
+IASL_BASE_URL="https://downloadmirror.intel.com/783534"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…"
diff --git a/util/crossgcc/patches/acpica-unix-20240321_iasl.patch b/util/crossgcc/patches/acpica-unix-20230628_iasl.patch
similarity index 100%
rename from util/crossgcc/patches/acpica-unix-20240321_iasl.patch
rename to util/crossgcc/patches/acpica-unix-20230628_iasl.patch
diff --git a/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
new file mode 100644
index 0000000..9b676bb
--- /dev/null
+++ b/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
@@ -0,0 +1 @@
+3b893fb771cf3fbd3531de3036e1a5bfc624c9d2 tarballs/acpica-unix-20230628.tar.gz
diff --git a/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
deleted file mode 100644
index e7b7afe..0000000
--- a/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-19f5b03de6de059a95432d17ed24095262a97aba tarballs/acpica-unix-20240321.tar.gz
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Attention is currently required from: Jan Philipp Groß, Máté Kukri.
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Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
......................................................................
Patch Set 15:
(2 comments)
File src/mainboard/asrock/z97e-itx_ac/Kconfig:
https://review.coreboot.org/c/coreboot/+/82760/comment/fe4ac5f6_a2d7879f?us… :
PS15, Line 1: ## SPDX-License-Identifier: GPL-2.0-or-later
> Add blank line here.
Let's do that at some point later. Done.
File src/mainboard/asrock/z97e-itx_ac/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/82760/comment/d7420bfd_951557bf?us… :
PS15, Line 18: /* global NVS and variables. */
> Seems superfluous. Please remove.
Let's do that at some point later. Done.
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Change subject: arch/x86: Decouple socket type from SoC type
......................................................................
Patch Set 1: Code-Review+1
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Change subject: cpu/intel: Add socket types
......................................................................
Patch Set 1: Code-Review+1
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Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
Thanks Max for letting us know.
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Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83296/comment/b1328bba_ef24766c?us… :
PS3, Line 12: Coreboot
> change to lowercase to pass testing.
Done
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