coreboot-gerrit July 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Martin Roth (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth, Maximilian Brune. Martin Roth has uploaded a new patch set (#4) to the change originally created by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc. Reason for revert: The version downloaded does not match the version that is printed out when executing `iasl --version`. coreboot notices that and refuses to compile QEMU-Q35 mainboard. I tested it on 2 different PCs. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20230628_iasl.patch A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum D util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum 4 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83296/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Martin Roth (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth, Maximilian Brune. Martin Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83296/comment/13d55f57_fb413553?us… : PS3, Line 12: Coreboot change to lowercase to pass testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:46:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Martin Roth (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth, Maximilian Brune. Martin Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > is there a way to compile from git as we do for 3rdparty? Yes, but we'll have to update the script. In the meantime, I say we push this revert. It doesn't actually change the version being used because the update didn't actually change the version. If the tarball on the intel site gets updated to be correct, the build script going to fail because it doesn't match the hash of the incorrect version. We have the incorrect version on our site as well. So does debian, in their sources, which really surprised me. I would have thought that they'd generate a new tarball based on their own sources, but they just used the one intel released. -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:45:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Martin Roth (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Felix Singer, Martin L Roth, Maximilian Brune. Martin Roth has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:38:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: src/soc/intel/common/block/imc: add Integrated Memory Controller driver
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Jérémy Compostella has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: src/soc/intel/common/block/imc: add Integrated Memory Controller driver ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/imc/imc.c: https://review.coreboot.org/c/coreboot/+/83320/comment/72e19021_b0d4e4d2?us… : PS2, Line 20: (1 << 29) BIT(29) -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:36:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: add CPU and PCIe definitions for SNR
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Jérémy Compostella has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email ) Change subject: add CPU and PCIe definitions for SNR ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: - Isn't it an EDS could you could reference in the commit message ? - The list of files touched is short compared to https://review.coreboot.org/c/coreboot/+/62581 which was for Meteor Lake. Is this expected for SNR ? File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/83314/comment/e7a8663b_68e63d3d?us… : PS1, Line 86: #define CPUID_SNOWRIDGE_A0 0x80660 Isn't it missing an extra tab for indentation ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Gerrit-Change-Number: 83314 Gerrit-PatchSet: 1 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: vc/intel/fsp/snr: Add FSP headers for Snow Ridge SoC
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Jérémy Compostella has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email ) Change subject: vc/intel/fsp/snr: Add FSP headers for Snow Ridge SoC ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Could you add the FSP version. Example: 3f0a9579a8fbe3d52b0b82d410500156d5f3e8ba -- To view, visit https://review.coreboot.org/c/coreboot/+/83192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc Gerrit-Change-Number: 83192 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 03 Jul 2024 17:26:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rex: Set cnvi_wifi bluetooth companion device
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83299?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Set cnvi_wifi bluetooth companion device ...................................................................... mb/google/rex: Set cnvi_wifi bluetooth companion device To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/deku/overridetree.cb M src/mainboard/google/rex/variants/karis/overridetree.cb M src/mainboard/google/rex/variants/ovis/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/mainboard/google/rex/variants/screebo/overridetree.cb 5 files changed, 5 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index fcacbea..0d8eefe 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -325,6 +325,7 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use usb2_port10 as bluetooth_companion device generic 0 on end end end diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index c74b51c..57c7c73 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -347,6 +347,7 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use usb2_port10 as bluetooth_companion device generic 0 on probe WIFI_TYPE WIFI_CNVI end diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 2c49c4c..ddedd1e 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -295,6 +295,7 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use usb2_port10 as bluetooth_companion device generic 0 on end end end diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 1d1957a..145ce44 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -421,6 +421,7 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use usb2_port10 as bluetooth_companion device generic 0 on probe WIFI WIFI_CNVI end diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index c66b5cb..59984e5 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -408,6 +408,7 @@ register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" + use usb2_port10 as bluetooth_companion device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/83299?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e Gerrit-Change-Number: 83299 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81790?usp=email ) Change subject: drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC ...................................................................... drivers/wifi: Support 320Mhz Bandwidth Enablement per MCC Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 58 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index e303589..13120d4 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -539,6 +539,43 @@ acpigen_write_package_end(); } +static void sar_emit_wbem(const struct wbem_profile *wbem) +{ + if (wbem == NULL) + return; + + /* + * Name ("WBEM", Package() { + * { + * Revision, + * Package() + * { + * DomainType, // 0x7:WiFi + * bandwidth_320mhz_country_enablement // 0 Disabled + * // 1 Japan Enabled + * // 2 South Korea Enabled + * // 3 Japan + South Korea Enabled + * } + } }) + */ + if (wbem->revision != WBEM_REVISION) { + printk(BIOS_ERR, "Unsupported WBEM table revision: %d\n", + wbem->revision); + return; + } + + acpigen_write_name("WBEM"); + acpigen_write_package(2); + acpigen_write_dword(wbem->revision); + + acpigen_write_package(2); + acpigen_write_dword(DOMAIN_TYPE_WIFI); + acpigen_write_dword(wbem->bandwidth_320mhz_country_enablement); + + acpigen_write_package_end(); + acpigen_write_package_end(); +} + static void emit_sar_acpi_structures(const struct device *dev, struct dsm_profile *dsm, struct bsar_profile *bsar, bool *bsar_loaded) { @@ -562,6 +599,7 @@ sar_emit_wgds(sar_limits.wgds); sar_emit_ppag(sar_limits.ppag); sar_emit_wtas(sar_limits.wtas); + sar_emit_wbem(sar_limits.wbem); /* copy the dsm data to be later used for creating _DSM function */ if (sar_limits.dsm != NULL) diff --git a/src/include/sar.h b/src/include/sar.h index 7c1b95d..5968645 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -9,9 +9,10 @@ #define MAX_DENYLIST_ENTRY 16 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 6 +#define MAX_PROFILE_COUNT 7 #define MAX_SAR_REVISION 2 #define BSAR_REVISION 1 +#define WBEM_REVISION 0 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 #define SAR_REV0_SUBBANDS_COUNT 5 @@ -73,6 +74,11 @@ uint8_t le_lr_modulation; } __packed; +struct wbem_profile { + uint8_t revision; + uint32_t bandwidth_320mhz_country_enablement; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -88,6 +94,7 @@ struct avg_profile *wtas; struct dsm_profile *dsm; struct bsar_profile *bsar; + struct wbem_profile *wbem; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 8195886..50c59d5 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -102,6 +102,14 @@ return sizeof(struct bsar_profile); } +static int wbem_table_size(const struct wbem_profile *wbem) +{ + if (wbem == NULL) + return 0; + + return sizeof(struct wbem_profile); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -154,6 +162,7 @@ expected_sar_bin_size += sar_avg_table_size(sar_limits->wtas); expected_sar_bin_size += dsm_table_size(sar_limits->dsm); expected_sar_bin_size += bsar_table_size(sar_limits->bsar); + expected_sar_bin_size += wbem_table_size(sar_limits->wbem); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "Invalid SAR size, expected: %zu, obtained: %zu\n", @@ -220,6 +229,7 @@ * [WTAS_REVISION, WTAS_DATA] * [DSM_RETURN_VALUES] * [BSAR_REVISION,IPML,LB,BR,EDR2,EDR3,LE,LE2,LE_LR] + * [WBEM_REVISION, WBEM_DATA] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be @@ -259,6 +269,8 @@ * [Enable/disable the TAS feature] * [Number of blocked countries that are not approved by the OEM to support this feature] * [deny_list_entry_<1-16>: ISO country code to block] + * [WBEM_DATA] = + * [Enable or disable 320MHZ Bandwidth for Japan, SouthKorea] */ int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Gerrit-Change-Number: 81790 Gerrit-PatchSet: 13 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Dinesh Sharma <dinesh.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: drivers/wifi: Support Bluetooth Regulator Domain Settings
by Jérémy Compostella (Code Review) 03 Jul '24

03 Jul '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83200?usp=email ) Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings ...................................................................... drivers/wifi: Support Bluetooth Regulator Domain Settings The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 4 files changed, 105 insertions(+), 5 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index d3da51b..e303589 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -15,8 +15,9 @@ #include "wifi.h" #include "wifi_private.h" -/* WIFI Domain type */ +/* Domain type */ #define DOMAIN_TYPE_WIFI 0x7 +#define DOMAIN_TYPE_BLUETOOTH 0x12 /* Maximum number DSM UUID bifurcations in _DSM */ #define MAX_DSM_FUNCS 2 @@ -489,9 +490,59 @@ acpigen_write_package_end(); } -static void emit_sar_acpi_structures(const struct device *dev, struct dsm_profile *dsm) +static void sar_emit_brds(const struct bsar_profile *bsar) { - union wifi_sar_limits sar_limits = {{NULL, NULL, NULL, NULL, NULL} }; + size_t package_size, table_size; + const uint8_t *set; + + /* + * Name ("BRDS", Package () { + * Revision, + * Package () { + * Domain Type, // 0x12:Bluetooth + * Bluetooth SAR BIOS, // BIOS SAR Enable/disable + * Bluetooth Increase Power Mode // SAR Limitation Enable/disable + * Bluetooth SAR Power Restriction, // 00000000 - 0dBm + * // 11111111 - 31.875dBm + * // (Step 0.125dBm) + * Bluetooth SAR Table // SAR Tx power limit table + * } + * }) + */ + if (bsar->revision != BSAR_REVISION) { + printk(BIOS_ERR, "Unsupported BSAR table revision: %d\n", + bsar->revision); + return; + } + + acpigen_write_name("BRDS"); + acpigen_write_package(2); + acpigen_write_dword(bsar->revision); + + table_size = sizeof(*bsar) - + offsetof(struct bsar_profile, sar_lb_power_restriction); + /* + * Emit 'Domain Type' + 'Dynamic SAR Enable' + 'Increase Power Mode' + * + ('SAR Power Restriction' + SAR table). + */ + package_size = 1 + 1 + 1 + table_size; + acpigen_write_package(package_size); + acpigen_write_dword(DOMAIN_TYPE_BLUETOOTH); + acpigen_write_dword(1); + acpigen_write_dword(bsar->increased_power_mode_limitation); + + set = (const uint8_t *)&bsar->sar_lb_power_restriction; + for (int i = 0; i < table_size; i++) + acpigen_write_byte(set[i]); + + acpigen_write_package_end(); + acpigen_write_package_end(); +} + +static void emit_sar_acpi_structures(const struct device *dev, struct dsm_profile *dsm, + struct bsar_profile *bsar, bool *bsar_loaded) +{ + union wifi_sar_limits sar_limits = {0}; /* * If device type is PCI, ensure that the device has Intel vendor ID. CBFS SAR and SAR @@ -516,6 +567,12 @@ if (sar_limits.dsm != NULL) memcpy(dsm, sar_limits.dsm, sizeof(struct dsm_profile)); + /* copy the bsar data to be later used for creating Bluetooth BRDS method */ + if (sar_limits.bsar != NULL) { + memcpy(bsar, sar_limits.bsar, sizeof(struct bsar_profile)); + *bsar_loaded = true; + } + free(sar_limits.sar); } @@ -576,11 +633,14 @@ struct dsm_uuid dsm_ids[MAX_DSM_FUNCS]; /* We will need a copy dsm data to be used later for creating _DSM function */ struct dsm_profile dsm = {0}; + /* We will need a copy of bsar data to be used later for creating BRDS function */ + struct bsar_profile bsar = {0}; + bool bsar_loaded = false; uint8_t dsm_count = 0; /* Fill Wifi SAR related ACPI structures */ if (CONFIG(USE_SAR)) { - emit_sar_acpi_structures(dev, &dsm); + emit_sar_acpi_structures(dev, &dsm, &bsar, &bsar_loaded); if (dsm.supported_functions != 0) { for (int i = 1; i < ARRAY_SIZE(wifi_dsm_callbacks); i++) @@ -618,6 +678,19 @@ acpigen_write_scope_end(); /* Scope */ + /* Fill Bluetooth companion SAR related ACPI structures */ + if (bsar_loaded && is_dev_enabled(config->bluetooth_companion)) { + const char *path = acpi_device_path(config->bluetooth_companion); + if (path) { /* Bluetooth device under USB Hub scope or PCIe root port */ + acpigen_write_scope(path); + sar_emit_brds(&bsar); + acpigen_write_scope_end(); + } else { + printk(BIOS_ERR, "Failed to get %s Bluetooth companion ACPI path\n", + dev_path(dev)); + } + } + printk(BIOS_INFO, "%s: %s %s\n", scope, dev->chip_ops ? dev->chip_ops->name : "", dev_path(dev)); } diff --git a/src/drivers/wifi/generic/chip.h b/src/drivers/wifi/generic/chip.h index 2729a35..302dd14 100644 --- a/src/drivers/wifi/generic/chip.h +++ b/src/drivers/wifi/generic/chip.h @@ -19,6 +19,9 @@ * SoC code propagates this value the applicable FSP UPD. */ bool enable_cnvi_ddr_rfim; + + /* Pointer to the Bluetooth companion device */ + DEVTREE_CONST struct device *bluetooth_companion; }; #endif /* _GENERIC_WIFI_H_ */ diff --git a/src/include/sar.h b/src/include/sar.h index c201cea..7c1b95d 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -9,8 +9,9 @@ #define MAX_DENYLIST_ENTRY 16 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 5 +#define MAX_PROFILE_COUNT 6 #define MAX_SAR_REVISION 2 +#define BSAR_REVISION 1 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 #define SAR_REV0_SUBBANDS_COUNT 5 @@ -60,6 +61,18 @@ uint32_t enablement_11be; }; +struct bsar_profile { + uint8_t revision; + uint8_t increased_power_mode_limitation; + uint8_t sar_lb_power_restriction; + uint8_t br_modulation; + uint8_t edr2_modulation; + uint8_t edr3_modulation; + uint8_t le_modulation; + uint8_t le2_mhz_modulation; + uint8_t le_lr_modulation; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -74,6 +87,7 @@ struct gain_profile *ppag; struct avg_profile *wtas; struct dsm_profile *dsm; + struct bsar_profile *bsar; }; void *profile[MAX_PROFILE_COUNT]; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index c42bf65..8195886 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -94,6 +94,14 @@ return sizeof(struct dsm_profile); } +static int bsar_table_size(const struct bsar_profile *bsar) +{ + if (bsar == NULL) + return 0; + + return sizeof(struct bsar_profile); +} + static bool valid_legacy_length(size_t bin_len) { if (bin_len == LEGACY_SAR_WGDS_BIN_SIZE) @@ -145,6 +153,7 @@ expected_sar_bin_size += gain_table_size(sar_limits->ppag); expected_sar_bin_size += sar_avg_table_size(sar_limits->wtas); expected_sar_bin_size += dsm_table_size(sar_limits->dsm); + expected_sar_bin_size += bsar_table_size(sar_limits->bsar); if (sar_bin_size != expected_sar_bin_size) { printk(BIOS_ERR, "Invalid SAR size, expected: %zu, obtained: %zu\n", @@ -210,6 +219,7 @@ * [PPAG_REVISION,MODE,CHAINS_COUNT,SUBBANDS_COUNT<PPAG_DATA>] * [WTAS_REVISION, WTAS_DATA] * [DSM_RETURN_VALUES] + * [BSAR_REVISION,IPML,LB,BR,EDR2,EDR3,LE,LE2,LE_LR] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be -- To view, visit https://review.coreboot.org/c/coreboot/+/83200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Gerrit-Change-Number: 83200 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dinesh.sharma(a)intel.com

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