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Felix Singer has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83327?usp=email )
Change subject: mb/intel/beechnutcity_crb: Update SMBIOS type 0,1,2,3 info
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/intel/beechnutcity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/83327/comment/3a27d903_1eebb2ea?us… :
PS1, Line 29: config MAINBOARD_VENDOR
: string
: default "Intel Corporation"
Not needed. The vendor is configured in the Kconfig from mainboard/intel.
https://review.coreboot.org/c/coreboot/+/83327/comment/8f014d62_41721835?us… :
PS1, Line 37: config MAINBOARD_SERIAL_NUMBER
: string
: d
Seems superfluous too. A dummy serial number is configured in the top-level Kconfig at src/Kconfig.
--
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Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/83332?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp: Add smbios_get_max_socket
......................................................................
soc/intel/xeon_sp: Add smbios_get_max_socket
TEST=Boot on intel/avenuecity CRB
SMBIOS type 4 and type 7 entries are created according to
CPU counts on multiple cpu platforms
Change-Id: I10a20cf94821d4b6fa7af2637969724be1e3bf3d
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/util.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83332/1
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 4dbe7a4..9009666 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -11,6 +11,7 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
+#include <smbios.h>
#include <soc/chip_common.h>
#include <soc/pch_pci_devs.h>
#include <soc/pci_devs.h>
@@ -90,6 +91,11 @@
return get_iio_uds()->SystemStatus.numCpus;
}
+unsigned int smbios_get_max_socket(void)
+{
+ return soc_get_num_cpus();
+}
+
union p2sb_bdf soc_get_hpet_bdf(void)
{
if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
--
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Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/83331?usp=email
to review the following change.
Change subject: lib/smbios: Create SMBIOS type 4 entry
......................................................................
lib/smbios: Create SMBIOS type 4 entry
One smbios type 4 should be provided for each CPU instance.
Create SMBIOS type 4 entry according to socket number, with a
default value of 1.
TEST=Boot on intel/archercity CRB
No changes in boot log and 'dmidecode' result under centos
Change-Id: Ia47fb7c458f9e89ae63ca64c0d6678b55c9d9d37
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/include/smbios.h
M src/lib/smbios.c
2 files changed, 11 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/83331/1
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 8ef37d8..ec776b1 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -74,6 +74,7 @@
unsigned int smbios_cpu_get_max_speed_mhz(void);
unsigned int smbios_cpu_get_current_speed_mhz(void);
unsigned int smbios_cpu_get_voltage(void);
+unsigned int smbios_get_max_socket(void);
const char *smbios_mainboard_manufacturer(void);
const char *smbios_mainboard_product_name(void);
diff --git a/src/lib/smbios.c b/src/lib/smbios.c
index ca71e3b..76d999f 100644
--- a/src/lib/smbios.c
+++ b/src/lib/smbios.c
@@ -443,6 +443,11 @@
return 0; /* Unknown */
}
+unsigned int __weak smbios_get_max_socket(void)
+{
+ return 1;
+}
+
static int smbios_write_type1(unsigned long *current, int handle)
{
struct smbios_type1 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_INFORMATION,
@@ -1233,9 +1238,11 @@
handle++;
update_max(len, max_struct_size, smbios_write_type3(¤t, handle++));
- struct smbios_type4 *type4 = (struct smbios_type4 *)current;
- update_max(len, max_struct_size, smbios_write_type4(¤t, handle++));
- len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4);
+ for (unsigned int s = 0; s < smbios_get_max_socket(); s++) {
+ struct smbios_type4 *type4 = (struct smbios_type4 *)current;
+ update_max(len, max_struct_size, smbios_write_type4(¤t, handle++));
+ len += smbios_write_type7_cache_parameters(¤t, &handle, &max_struct_size, type4);
+ }
update_max(len, max_struct_size, smbios_write_type11(¤t, &handle));
if (CONFIG(ELOG))
update_max(len, max_struct_size,
--
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Hello Jincheng Li,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/83330?usp=email
to review the following change.
Change subject: arch/x86: Decouple socket type from SoC type
......................................................................
arch/x86: Decouple socket type from SoC type
Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/arch/x86/smbios.c
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83330/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 4fa8612..97d5f24 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -52,16 +52,16 @@
return PROCESSOR_UPGRADE_SOCKET_MPGA604;
if (CONFIG(CPU_INTEL_SOCKET_LGA775))
return PROCESSOR_UPGRADE_SOCKET_LGA775;
- if (CONFIG(SOC_INTEL_ALDERLAKE))
+ if (CONFIG(CPU_INTEL_SOCKET_LGA1700))
return PROCESSOR_UPGRADE_SOCKET_LGA1700;
- if (CONFIG(SOC_INTEL_METEORLAKE))
- return PROCESSOR_UPGRADE_OTHER;
- if (CONFIG(SOC_INTEL_SKYLAKE_SP))
- return PROCESSOR_UPGRADE_SOCKET_LGA3647_1;
- if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
+ if (CONFIG(CPU_INTEL_SOCKET_LGA4189))
return PROCESSOR_UPGRADE_SOCKET_LGA4189;
- if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
+ if (CONFIG(CPU_INTEL_SOCKET_LGA4677))
return PROCESSOR_UPGRADE_SOCKET_LGA4677;
+ if (CONFIG(CPU_INTEL_SOCKET_LGA3647_1))
+ return PROCESSOR_UPGRADE_SOCKET_LGA3647_1;
+ if (CONFIG(CPU_INTEL_SOCKET_OTHER))
+ return PROCESSOR_UPGRADE_OTHER;
return PROCESSOR_UPGRADE_UNKNOWN;
}
--
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Felix Singer has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )
Change subject: src/soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83321/comment/f9156a20_73c54479?us… :
PS3, Line 7: src/
Remove "src"
File src/soc/intel/snowridge/COPYING-NOTICE:
PS3:
This probably does not belong here.
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