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Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71 TEST=Validated on qualcomm sc7180 development board
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/qc_blobs/+/83305/comment/04447667_237ae92e?us… :
PS1, Line 8: TEST=Validated on qualcomm sc7180 development board
Please add a blank line above.
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Change subject: drivers/wifi: Support Bluetooth Regulator Domain Settings
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Patch Set 10:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/83200/comment/5634df97_d30e36ed?us… :
PS9, Line 493: bsar
> > The other functions do receive a potentially NULL pointer. […]
Since this is the public repository, the static analyzer will runs once code is merged.
The static analyzer follows the code path. Therefore it cannot report any NULL pointer issue as is just impossible with the current implementation.
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Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Michał Żygowski.
Krystian Hebel has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email )
Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
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Patch Set 12:
(4 comments)
File src/mainboard/novacustom/mtl-h/Kconfig:
https://review.coreboot.org/c/coreboot/+/82673/comment/59e257b3_2dbd1bb4?us… :
PS12, Line 69: 512
1024 for DDR5
File src/mainboard/novacustom/mtl-h/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82673/comment/dbea66dc_21d422b0?us… :
PS12, Line 61: register "device_count" = "3"
Why 3?
File src/mainboard/novacustom/mtl-h/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82673/comment/3b4fe2b9_865532e7?us… :
PS12, Line 3: #include <ec/dasharo/ec/commands.h>
: #include <ec/acpi/ec.h>
: #include <ec/dasharo/ec/acpi.h>
: #include <fmap.h>
: #include <lib.h>
: #include <mainboard/gpio.h>
: #include <security/vboot/vboot_common.h>
Not all of those are needed. It seems that only functions from `mainboard/gpio.h` and `ec/acpi.h` are used.
https://review.coreboot.org/c/coreboot/+/82673/comment/a9e0a074_6899c6d1?us… :
PS12, Line 43: params->CnviRfResetPinMux = 0x194CE404; // GPP_F04
Can those magic numbers be expressed as some macros from e.g. `gpio_defs.h` instead?
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> > Okay, but shouldn't they be the stock ones then? And then Google has a "custom" directory or somet […]
Fair enough. The problem with the header Kconfig is the memory info hobs differ in the Intel downloads; there's a Kconfig tied to that but it seems to break other things so the only way is to smush the directories together.
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Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> Okay, but shouldn't they be the stock ones then? And then Google has a "custom" directory or something like that for their version?
I just had a conversation with Felix about this issue. You are right that it would be better if Google could have their own directory for their FSP headers. The problem is that Google was the only company engaging with Intel during the pre-silicon to PRQ stage of SoC, so no one else needed to interact with the headers. However, it’s definitely possible to override the FSP header path (kconfig) with another directory if you want.
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