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Change subject: mb/google/brya: change NAU8825 config to fix headset button detection
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS4:
Thanks, shortened title and fixed commit ID.
Commit Message:
https://review.coreboot.org/c/coreboot/+/83472/comment/fd7bef7f_3d00fc2f?us… :
PS3, Line 7: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
> nit: please shorten the title.
Done
https://review.coreboot.org/c/coreboot/+/83472/comment/6e369c98_dfc3227f?us… :
PS3, Line 10: I349682a6fe3fe4848e4e86d9c446530a31b35875
> nit:no need the full hash.
Done
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Attention is currently required from: Dinesh Gehlot, Emilie Roberts, Kapil Porwal, Nick Vaccaro.
Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83472?usp=email
to look at the new patch set (#4).
Change subject: mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter
......................................................................
mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter
Fixes a pmc_mux port mapping error introduced in coreboot commit
4fa8354.
Mithrax and felwinter do not have sequential mux_conn[X] to connY mappings which led to the kernel subsystem linking between Type C connectorand USB mux to be incorrect. The previous patch attempted to fix this by changing the custom_pld layout. However this broke USB usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur(a)google.com>
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
2 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83472/4
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Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83469?usp=email )
Change subject: superio/ite,mb: Switch the mainboards' code to the new ITE GPIO driver
......................................................................
superio/ite,mb: Switch the mainboards' code to the new ITE GPIO driver
Refactor mainboards' code to use the new GPIO and remove any custom
driver in the respective ITE SIO chip directory.
Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/mainboard/google/beltino/variants/mccloud/led.c
M src/mainboard/google/beltino/variants/tricky/led.c
M src/mainboard/google/jecht/led.c
M src/mainboard/hp/pro_3500_series/led.c
M src/mainboard/samsung/stumpy/early_init.c
M src/mainboard/samsung/stumpy/smihandler.c
M src/superio/ite/it8659e/it8659e.h
M src/superio/ite/it8772f/Makefile.mk
D src/superio/ite/it8772f/early_init.c
M src/superio/ite/it8772f/it8772f.h
10 files changed, 72 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83469/2
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Eric Lai has posted comments on this change by Emilie Roberts. ( https://review.coreboot.org/c/coreboot/+/83472?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83472/comment/943c2dcb_1a446c32?us… :
PS3, Line 7: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
nit: please shorten the title.
https://review.coreboot.org/c/coreboot/+/83472/comment/01dc4f51_5c7cc9dd?us… :
PS3, Line 10: I349682a6fe3fe4848e4e86d9c446530a31b35875
nit:no need the full hash.
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83472?usp=email
to look at the new patch set (#3).
Change subject: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
......................................................................
mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
Fixes a pmc_mux port mapping error introduced in corbeoot commit
I349682a6fe3fe4848e4e86d9c446530a31b35875.
Mithrax and felwinter do not have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connector and USB mux to be. The previous patch attempted to fix this
by changing the custom_pld layout. However this caused USB disk access
to break and to disable USB port usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur(a)google.com>
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
2 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83472/3
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83472?usp=email
to look at the new patch set (#2).
Change subject: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
......................................................................
mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
Fixes a pmc_mux port mapping error introduced in corbeoot commit
I349682a6fe3fe4848e4e86d9c446530a31b35875.
Mithrax and felwinter do not have have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connector and USB mux to be. The previous patch attempted to fix this
by changing the custom_pld layout. However this caused USB disk access
to break and to disable USB port usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur(a)google.com>
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
2 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83472/2
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Change subject: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
......................................................................
Patch Set 1: Code-Review+2
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Emilie Roberts has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83472?usp=email )
Change subject: mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
......................................................................
mb/google/brya: Fix pmc_mux port in ec/google/chromeec for mithrax and felwinter
Fixes a pmc_mux port mapping error introduced in corbeoot commit
I349682a6fe3fe4848e4e86d9c446530a31b35875.
Mithrax and felwinter do not have have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connector and USB mux to be. The previous patch attempted to fix this
by changing the custom_pld layout. However this caused USB disk access
to break and to disable USB port usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur(a)google.com>
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
2 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83472/1
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index 61cb500..8b5dd0d 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -358,13 +358,13 @@
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
- use usb2_port3 as usb2_port
- use tcss_usb3_port3 as usb3_port
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port2 as usb3_port
device generic 2 alias conn2 on end
end
chip drivers/intel/pmc_mux/conn
- use usb2_port2 as usb2_port
- use tcss_usb3_port2 as usb3_port
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
@@ -377,16 +377,16 @@
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
register "usb_lpm_incapable" = "true"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
end
end
end
@@ -398,15 +398,15 @@
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
- device ref usb2_port2 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 61344d7..70a4423 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -306,13 +306,13 @@
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
- use usb2_port3 as usb2_port
- use tcss_usb3_port3 as usb3_port
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port2 as usb3_port
device generic 2 alias conn2 on end
end
chip drivers/intel/pmc_mux/conn
- use usb2_port2 as usb2_port
- use tcss_usb3_port2 as usb3_port
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
@@ -325,16 +325,16 @@
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
register "usb_lpm_incapable" = "true"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
end
end
end
@@ -346,15 +346,15 @@
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
- device ref usb2_port2 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
@@ -365,7 +365,7 @@
register "desc" = ""USB2 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
@@ -379,7 +379,7 @@
register "desc" = ""USB3 Type-A Port A0 (DB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
- register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))"
device ref usb3_port1 on end
end
end
--
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Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Gerrit-Change-Number: 83472
Gerrit-PatchSet: 1
Gerrit-Owner: Emilie Roberts <hadrosaur(a)google.com>