coreboot-gerrit July 2024

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[L] Change in coreboot[main]: superio/ite/common: Add common driver for GPIO and LED configuration
by Michał Żygowski (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Nicholas Sudsgaard, Nico Huber. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83355?usp=email ) Change subject: superio/ite/common: Add common driver for GPIO and LED configuration ...................................................................... Patch Set 3: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83355/comment/6a22d92c_1dacb046?us… : PS1, Line 22: - Refactors the mainboards' code to use the new driver where possible > When a patch has hundreds of lines and a list of things it does […] Split into 3: - this one - CB:83468 (enabling the driver for in chip Kconfig) - CB:83469 (MB code refactoring) File src/mainboard/google/beltino/variants/mccloud/led.c: https://review.coreboot.org/c/coreboot/+/83355/comment/4f992d5c_c32717cf?us… : PS1, Line 18: ITE_LED_SHORT_PULSE_DISABLE, : ITE_LED_PINMAP_CLEAR_DISABLE, : ITE_LED_OUTPUT_LOW_DISABLE, : ITE_LED_FREQ_1HZ); > Random thought: Making the enum values masks (i.e. with the 1 shifted already) […] I have added gpio_ctrl and led_ctrl for these properties/flags, although I have left the frequency as a separate parameter. File src/mainboard/samsung/stumpy/smihandler.c: https://review.coreboot.org/c/coreboot/+/83355/comment/af5b83d5_603ac0df?us… : PS1, Line 25: ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20); > Yes, setup_sio_gpios already does it and further writes should not be necessary. Done in CB:83469 https://review.coreboot.org/c/coreboot/+/83355/comment/9553f431_eb7bce44?us… : PS1, Line 39: ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20); > Same. Done in CB:83469 https://review.coreboot.org/c/coreboot/+/83355/comment/a3de068c_7f40d524?us… : PS1, Line 49: ITE_LED_FREQ_1HZ); > Right, enabling SIMPLE_IO_MODE in the ite_gpio_setup call should already disable the LED blinking fu […] Done in CB:83469 File src/superio/ite/common/gpio.c: https://review.coreboot.org/c/coreboot/+/83355/comment/c20e78a2_9a0f4b7b?us… : PS1, Line 16: This ITE SIO GPIO driver support up to 10 GPIO sets > "ITE SIO GPIO drivers only support up to 10 GPIO sets" sounds more natural as an error message. Changed per suggestion https://review.coreboot.org/c/coreboot/+/83355/comment/2ab25276_dd42fe53?us… : PS1, Line 130: */ > Right, I will revisit these datasheets and fix Added the function which checks for the register presence like for the other 2 registers. Haven't found any other chips which would have some oddities here. File src/superio/ite/common/ite_gpio.h: https://review.coreboot.org/c/coreboot/+/83355/comment/e415e5f0_f3415c81?us… : PS1, Line 15: ITE_GPIO_PULLUP_DIS, : ITE_GPIO_PULLUP_EN > To keep the naming consistent with the other enums. […] It has been converted to a single flag: ITE_GPIO_PULLUP_ENABLE https://review.coreboot.org/c/coreboot/+/83355/comment/41548814_33b25d60?us… : PS1, Line 63: ITE_LED_FREQ_2Hz_DUTY_50 = 3, : ITE_LED_FREQ_0P25HZ_DUTY_25 = 4, : ITE_LED_FREQ_0P25HZ_DUTY_75 = 5, : ITE_LED_FREQ_0P125HZ_DUTY_25 = 6, : ITE_LED_FREQ_0P125Hz_DUTY_75 = 7, : ITE_LED_FREQ_0P4Hz_DUTY_20 = 8, : ITE_LED_FREQ_0P5Hz_DUTY_50 = 16, : ITE_LED_FREQ_0P125Hz_DUTY_50 = 24, > Is there a reason the 'z' is not capitalized for some of these enums? […] Applied. File src/superio/ite/it8772f/it8772f.h: https://review.coreboot.org/c/coreboot/+/83355/comment/01c5a181_ae782c65?us… : PS1, Line 16: : /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ : #define IT8772F_GPIO_REG_POLARITY(x) (0xb0 + (x)) : : /* GPIO Internal Pull-up: 1: Enable, 0: Disable */ : #define IT8772F_GPIO_REG_PULLUP(x) (0xb8 + (x)) : : /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ : #define IT8772F_GPIO_REG_ENABLE(x) (0xc0 + (x)) : : /* GPIO Mode: 0: input mode, 1: output mode */ : #define IT8772F_GPIO_REG_OUTPUT(x) (0xc8 + (x)) : > Forgot to leave IT8772F_GPIO_REG_SELECT only. […] Removed in CB:83469 ITE_GPIO_REG_SELECT moved to superio/ite/common/ite_gpio.h in this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/83355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Gerrit-Change-Number: 83355 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Mon, 15 Jul 2024 10:49:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>

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[M] Change in coreboot[main]: mb/google/brox/var/greenbayupoc: update ALC236 verb table
by Terry Cheong (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Derek Huang, Terry Cheong. Terry Cheong has posted comments on this change by Garen Wu. ( https://review.coreboot.org/c/coreboot/+/83465?usp=email ) Change subject: mb/google/brox/var/greenbayupoc: update ALC236 verb table ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83465?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df Gerrit-Change-Number: 83465 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Terry Cheong <htcheong(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Terry Cheong <htcheong(a)google.com> Gerrit-Comment-Date: Mon, 15 Jul 2024 10:47:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: superio/ite,mb: Switch the mainboards' code to the new ITE GPIO driver
by Michał Żygowski (Code Review) 15 Jul '24

15 Jul '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83469?usp=email ) Change subject: superio/ite,mb: Switch the mainboards' code to the new ITE GPIO driver ...................................................................... superio/ite,mb: Switch the mainboards' code to the new ITE GPIO driver Refactor mainboards' code to use the new GPIO and remove any custom driver in the respective ITE SIO chip directory. Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/jecht/led.c M src/mainboard/hp/pro_3500_series/led.c M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c M src/superio/ite/it8659e/it8659e.h M src/superio/ite/it8772f/Makefile.mk D src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h 10 files changed, 72 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83469/1 diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index da5002f..04e17ec 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,17 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" void set_power_led(int state) { - it8772f_gpio_led(IT8772F_GPIO_DEV, - 1, /* set */ - 0x01, /* select */ - state == LED_BLINK ? 0x01 : 0x00, /* polarity */ - state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ - 0x01, /* output */ - state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ - SIO_GPIO_BLINK_GPIO10, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO10 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, ITE_GPIO_REG_SELECT(0), 0x01); + ite_gpio_setup(IT8772F_GPIO_DEV, 10, ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE, + state == LED_BLINK ? ITE_GPIO_POL_INVERT | ITE_GPIO_PULLUP_ENABLE + : ITE_GPIO_CONTROL_DEFAULT); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 10, ITE_GPIO_LED_1, + ITE_LED_FREQ_1HZ, ITE_LED_CONTROL_DEFAULT); } diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index 49d7918..b21e18e 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,17 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" void set_power_led(int state) { - it8772f_gpio_led(IT8772F_GPIO_DEV, - 2, /* set */ - 0xF7, /* select */ - state == LED_OFF ? 0x00 : 0x04, /* polarity */ - state == LED_BLINK ? 0x04 : 0x00, /* pullup/pulldown */ - 0x04, /* output */ - state == LED_BLINK ? 0x00 : 0x04, /* I/O function */ - SIO_GPIO_BLINK_GPIO22, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO22 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, ITE_GPIO_REG_SELECT(1), 0xf7); + ite_gpio_setup(IT8772F_GPIO_DEV, 22, ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE, + (state != LED_OFF ? ITE_GPIO_POL_INVERT : 0) | + (state == LED_BLINK ? ITE_GPIO_PULLUP_ENABLE : 0)); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 22, ITE_GPIO_LED_1, + ITE_LED_FREQ_1HZ, ITE_LED_CONTROL_DEFAULT); } diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 8a6a304..419ef44 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,25 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" void set_power_led(int state) { - int polarity; + u8 polarity; if (CONFIG(BOARD_GOOGLE_TIDUS)) { - polarity = state == LED_OFF ? 0x00 : 0x01; + polarity = state == LED_OFF ? ITE_GPIO_POL_INVERT : 0; } else { - polarity = state == LED_BLINK ? 0x01 : 0x00; + polarity = state == LED_BLINK ? ITE_GPIO_POL_INVERT : 0; } - it8772f_gpio_led(IT8772F_GPIO_DEV, - 1, /* set */ - 0x01, /* select */ - polarity, /* polarity */ - state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ - 0x01, /* output */ - state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ - SIO_GPIO_BLINK_GPIO10, - IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + /* Configure GPIO10 as power LED */ + ite_reg_write(IT8772F_GPIO_DEV, ITE_GPIO_REG_SELECT(0), 0x01); + ite_gpio_setup(IT8772F_GPIO_DEV, 10, ITE_GPIO_OUTPUT, + state == LED_BLINK ? ITE_GPIO_ALT_FN_MODE : ITE_GPIO_SIMPLE_IO_MODE, + (state == LED_BLINK ? ITE_GPIO_PULLUP_ENABLE : ITE_GPIO_CONTROL_DEFAULT) | + polarity); + ite_gpio_setup_led(IT8772F_GPIO_DEV, 10, ITE_GPIO_LED_1, + ITE_LED_CONTROL_DEFAULT, ITE_LED_FREQ_1HZ); } diff --git a/src/mainboard/hp/pro_3500_series/led.c b/src/mainboard/hp/pro_3500_series/led.c index 073f5f5..103763f 100644 --- a/src/mainboard/hp/pro_3500_series/led.c +++ b/src/mainboard/hp/pro_3500_series/led.c @@ -1,17 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> + #include "common_defines.h" #include "led.h" void set_power_led(int state) { - // Board has a dual color LED - it8772f_gpio_setup( - GPIO_DEV, - 2, /* set */ - 0xf3 | LED_BOTH, /* select, 0xf3 is default */ - state, /* polarity */ - 0x00, /* pullup */ - LED_BOTH, /* output */ - 0x00); /* enable */ + // Board has a dual color LED: GPIO22 and GPIO23 + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(1), 0xf3 | LED_BOTH); + ite_gpio_setup(GPIO_DEV, 22, ITE_GPIO_OUTPUT, ITE_GPIO_ALT_FN_MODE, + state & LED_WHITE ? ITE_GPIO_POL_INVERT : ITE_GPIO_CONTROL_DEFAULT); + ite_gpio_setup(GPIO_DEV, 23, ITE_GPIO_OUTPUT, ITE_GPIO_ALT_FN_MODE, + state & LED_YELLOW ? ITE_GPIO_POL_INVERT : ITE_GPIO_CONTROL_DEFAULT); } diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 852759e..e4b4020 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -5,6 +5,7 @@ #include <pc80/mc146818rtc.h> #include <bootmode.h> #include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> @@ -58,32 +59,40 @@ * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(GPIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); - + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(0), 0x05); + ite_gpio_setup(GPIO_DEV, 10, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); + ite_gpio_setup(GPIO_DEV, 12, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(GPIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); - + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(1), 0x04); + ite_gpio_setup(GPIO_DEV, 22, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(GPIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); - + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(2), 0x04); + ite_gpio_setup(GPIO_DEV, 32, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); /* * GPIO45 as LED_POWER# */ - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, - (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); - + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(3), 0x20); + ite_gpio_setup(GPIO_DEV, 45, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT | ITE_GPIO_PULLUP_ENABLE); + ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, ITE_LED_FREQ_1HZ, + ITE_LED_CONTROL_DEFAULT); /* * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(GPIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(GPIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); + ite_reg_write(GPIO_DEV, ITE_GPIO_REG_SELECT(4), 0x06); + ite_gpio_setup(GPIO_DEV, 51, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); + ite_gpio_setup(GPIO_DEV, 52, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_POL_INVERT); } void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index f9b9d3b..0b6e133 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -8,6 +8,8 @@ #include <northbridge/intel/sandybridge/sandybridge.h> /* Include for SIO helper functions */ +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> #include <superio/ite/it8772f/it8772f.h> #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) @@ -20,17 +22,14 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, - (0x1 << 5) /* output */, 0x00, /* 0 = Alternate function */ - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + ite_gpio_setup(GPIO_DEV, 45, ITE_GPIO_OUTPUT, ITE_GPIO_ALT_FN_MODE, + ITE_GPIO_POL_INVERT | ITE_GPIO_PULLUP_ENABLE); + ite_gpio_setup_led(GPIO_DEV, 45, ITE_GPIO_LED_1, ITE_LED_FREQ_1HZ, + ITE_LED_CONTROL_DEFAULT); break; - case ACPI_S5: - it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, - 0x00 /* polarity: non-inverting */, 0x00 /* 0 = pulldown */, - (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, - SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + ite_gpio_setup(GPIO_DEV, 45, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_CONTROL_DEFAULT); break; default: break; diff --git a/src/superio/ite/it8659e/it8659e.h b/src/superio/ite/it8659e/it8659e.h index 4fa91e9..f6eda07 100644 --- a/src/superio/ite/it8659e/it8659e.h +++ b/src/superio/ite/it8659e/it8659e.h @@ -11,24 +11,4 @@ #define IT8659E_GPIO 0x07 /* GPIO */ #define IT8659E_CIR 0x0A /* CIR */ -/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ -#define GPIO_REG_POLARITY(x) (0xb0 + (x)) -#define GPIO_POL_NO_INVERT 0 -#define GPIO_POL_INVERT 1 - -/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ -#define GPIO_REG_PULLUP(x) (0xb8 + (x)) -#define GPIO_PULLUP_DIS 0 -#define GPIO_PULLUP_EN 1 - -/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ -#define GPIO_REG_ENABLE(x) (0xc0 + (x)) -#define GPIO_ALT_FN 0 -#define GPIO_SIMPLE_IO 1 - -/* GPIO Mode: 0: input mode, 1: output mode */ -#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -#define GPIO_INPUT_MODE 0 -#define GPIO_OUTPUT_MODE 1 - #endif /* SUPERIO_ITE_IT8659E_H */ diff --git a/src/superio/ite/it8772f/Makefile.mk b/src/superio/ite/it8772f/Makefile.mk index a96a862..93ea16d 100644 --- a/src/superio/ite/it8772f/Makefile.mk +++ b/src/superio/ite/it8772f/Makefile.mk @@ -1,6 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later -bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c -romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c -smm-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c deleted file mode 100644 index efbb035..0000000 --- a/src/superio/ite/it8772f/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <arch/io.h> -#include <device/pnp_def.h> -#include <device/pnp_ops.h> - -#include "it8772f.h" -#include "../common/ite.h" - -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ - -/* NOTICE: This file is deprecated, use ite/common instead */ - -static void it8772f_enter_conf(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8772f_exit_conf(pnp_devfn_t dev) -{ - pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); -} - -/* Configure a set of GPIOs */ -void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, - u8 pullup, u8 output, u8 enable) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(dev); - pnp_set_logical_device(dev); - if (set < 5) { - pnp_write_config(dev, GPIO_REG_SELECT(set), select); - pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); - pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); - } - pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); - pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(dev); -} - -/* Configure LED GPIOs */ -void it8772f_gpio_led(pnp_devfn_t dev,int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable, u8 led_pin_map, u8 led_freq) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(dev); - pnp_set_logical_device(dev); - if (set < 5) { - pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); - pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); - pnp_write_config(dev, GPIO_REG_SELECT(set), select); - pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); - pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); - } - pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); - pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(dev); -} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 4df21c5..f286923 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -11,42 +11,4 @@ #define IT8772F_GPIO 0x07 /* GPIO */ #define IT8772F_IR 0x0a /* Consumer IR */ - -/* GPIO interface */ -#define IT8772F_GPIO_LED_BLINK1_PINMAP 0xf8 - -#define SIO_GPIO_BLINK_GPIO10 0x08 -#define SIO_GPIO_BLINK_GPIO22 0x12 -#define SIO_GPIO_BLINK_GPIO45 0x25 - -#define IT8772F_GPIO_LED_BLINK1_CONTROL 0xf9 - -#define IT8772F_GPIO_BLINK_FREQUENCY_4_HZ (0<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_HZ (1<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_4_HZ (2<<1) -#define IT8772F_GPIO_BLINK_FREQUENCY_1_8_HZ (3<<1) - -#define GPIO_REG_SELECT(x) (0x25 + (x)) - -/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ -#define GPIO_REG_POLARITY(x) (0xb0 + (x)) - -/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ -#define GPIO_REG_PULLUP(x) (0xb8 + (x)) - -/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ -#define GPIO_REG_ENABLE(x) (0xc0 + (x)) - -/* GPIO Mode: 0: input mode, 1: output mode */ -#define GPIO_REG_OUTPUT(x) (0xc8 + (x)) - -#include <device/pnp_type.h> -#include <stdint.h> - -void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, - u8 pullup, u8 output, u8 enable); - -void it8772f_gpio_led(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable, u8 led_pin_map, u8 led_freq); - #endif /* SUPERIO_ITE_IT8772F_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I707ee090ee2551b4935847e12ade678d36ff9302 Gerrit-Change-Number: 83469 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[M] Change in coreboot[main]: superio/ite: Enable common driver for GPIO and LED configuration
by Michał Żygowski (Code Review) 15 Jul '24

15 Jul '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83468?usp=email ) Change subject: superio/ite: Enable common driver for GPIO and LED configuration ...................................................................... superio/ite: Enable common driver for GPIO and LED configuration Enables the driver for ITE SIOs supporting the GPIO register layout (confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs withj unavailable datasheets are unmodified). Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM and must then provide the number of GPIO sets specific to a chip via SUPERIO_ITE_COMMON_NUM_GPIO_SETS. Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/ite/it8613e/Kconfig M src/superio/ite/it8659e/Kconfig M src/superio/ite/it8712f/Kconfig M src/superio/ite/it8718f/Kconfig M src/superio/ite/it8720f/Kconfig M src/superio/ite/it8721f/Kconfig M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8783ef/Kconfig M src/superio/ite/it8784e/Kconfig M src/superio/ite/it8786e/Kconfig 11 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/83468/1 diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..cc709ae 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -3,9 +3,18 @@ config SUPERIO_ITE_IT8613E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_LED_FREQ_5BIT select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8613E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8659e/Kconfig b/src/superio/ite/it8659e/Kconfig index 92ee4c1..43b8c95 100644 --- a/src/superio/ite/it8659e/Kconfig +++ b/src/superio/ite/it8659e/Kconfig @@ -3,8 +3,17 @@ config SUPERIO_ITE_IT8659E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + + +if SUPERIO_ITE_IT8659E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8712f/Kconfig b/src/superio/ite/it8712f/Kconfig index 0dfa524..81b3c62 100644 --- a/src/superio/ite/it8712f/Kconfig +++ b/src/superio/ite/it8712f/Kconfig @@ -3,3 +3,11 @@ config SUPERIO_ITE_IT8712F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM + +if SUPERIO_ITE_IT8712F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 5 + +endif diff --git a/src/superio/ite/it8718f/Kconfig b/src/superio/ite/it8718f/Kconfig index 65fcdab..c17bf41 100644 --- a/src/superio/ite/it8718f/Kconfig +++ b/src/superio/ite/it8718f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8718F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8718F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig index 338ed21..3625ef6 100644 --- a/src/superio/ite/it8720f/Kconfig +++ b/src/superio/ite/it8720f/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8720F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8720F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index ec22a2d..8c2e676 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -3,7 +3,15 @@ config SUPERIO_ITE_IT8721F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8721F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index be16a2d..c85e94a 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8728F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR + +if SUPERIO_ITE_IT8728F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 8 + +endif diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 8e9af54..6d7cf39 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,6 +3,7 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM @@ -11,3 +12,10 @@ select SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED select SUPERIO_ITE_ENV_CTRL_NO_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8772F + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8783ef/Kconfig b/src/superio/ite/it8783ef/Kconfig index e1d993f..da47e45 100644 --- a/src/superio/ite/it8783ef/Kconfig +++ b/src/superio/ite/it8783ef/Kconfig @@ -3,6 +3,14 @@ config SUPERIO_ITE_IT8783EF bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + +if SUPERIO_ITE_IT8783EF + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 6 + +endif diff --git a/src/superio/ite/it8784e/Kconfig b/src/superio/ite/it8784e/Kconfig index 66dd6c9..ba19459 100644 --- a/src/superio/ite/it8784e/Kconfig +++ b/src/superio/ite/it8784e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8784E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8784E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 216d6f5..ab4a92f 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -3,8 +3,16 @@ config SUPERIO_ITE_IT8786E bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_COMMON_GPIO_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + +if SUPERIO_ITE_IT8786E + +config SUPERIO_ITE_COMMON_NUM_GPIO_SETS + default 10 + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798 Gerrit-Change-Number: 83468 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[L] Change in coreboot[main]: superio/ite/common: Add common driver for GPIO and LED configuration
by Michał Żygowski (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Nico Huber. Hello Nicholas Sudsgaard, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83355?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: superio/ite/common: Add common driver for GPIO and LED configuration ...................................................................... superio/ite/common: Add common driver for GPIO and LED configuration Add a generic driver to configure GPIOs and LEDs on common ITE SuperIOs. The driver supports most ITE SuperIOs, except Embedded Controllers. The driver allows configuring every GPIO property with pin granularity. Verified against datasheets of all ITE SIOs currently supported by coreboot, except IT8721F (assumed to be the same as IT8720F), IT8623E and IT8629E. Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/ite/Makefile.mk M src/superio/ite/common/Kconfig A src/superio/ite/common/gpio.c A src/superio/ite/common/ite_gpio.h 4 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83355/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83355?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If610d2809b56c63444c3406c26fad412c94136a5 Gerrit-Change-Number: 83355 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>

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[XL] Change in coreboot[main]: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
by Michał Żygowski (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Felix Singer, Maciej Pijanowski, Nico Huber, Piotr Król. Hello Nico Huber, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80501?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670 ...................................................................... mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670 It is a new incoming Protectli product based on Alder Lake-P SoC. More details and documentation will be added later. TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670. Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- A src/mainboard/protectli/vault_adl_p/Kconfig A src/mainboard/protectli/vault_adl_p/Kconfig.name A src/mainboard/protectli/vault_adl_p/Makefile.mk A src/mainboard/protectli/vault_adl_p/acpi/superio.asl A src/mainboard/protectli/vault_adl_p/board_beep.c A src/mainboard/protectli/vault_adl_p/board_beep.h A src/mainboard/protectli/vault_adl_p/board_info.txt A src/mainboard/protectli/vault_adl_p/bootblock.c A src/mainboard/protectli/vault_adl_p/data.vbt A src/mainboard/protectli/vault_adl_p/devicetree.cb A src/mainboard/protectli/vault_adl_p/die.c A src/mainboard/protectli/vault_adl_p/dsdt.asl A src/mainboard/protectli/vault_adl_p/gpio.c A src/mainboard/protectli/vault_adl_p/gpio.h A src/mainboard/protectli/vault_adl_p/hda_verb.c A src/mainboard/protectli/vault_adl_p/mainboard.c A src/mainboard/protectli/vault_adl_p/romstage_fsp_params.c A src/mainboard/protectli/vault_adl_p/vboot-rwa.fmd 18 files changed, 1,268 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/80501/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/80501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e Gerrit-Change-Number: 80501 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Anastasios Koutian (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Angel Pons. Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83270/comment/89884f17_52769aa3?us… : PS5, Line 8: > Hmmm, that wasn't very accurate. More technically: The enable bit makes […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jul 2024 10:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasios Koutian <akoutian2(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Anastasios Koutian (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Anastasios Koutian, Angel Pons. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83270?usp=email to look at the new patch set (#7). Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... cpu/intel/model_206ax: Allow package power limit clamping Setting the clamp bit allows the CPU to operate below the highest non-turbo frequency in order to obey the power limit. Tested on ThinkPad T420 with the i7-3940XM. Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com> --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83270/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
by Anastasios Koutian (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Angel Pons, Nico Huber. Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email ) Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration ...................................................................... Patch Set 6: (4 comments) File src/cpu/intel/model_206ax/chip.h: https://review.coreboot.org/c/coreboot/+/83271/comment/a46fe5d5_2c2f43b1?us… : PS5, Line 63: acrive > typo: ac**t**ive Done File src/cpu/intel/model_206ax/model_206ax.h: https://review.coreboot.org/c/coreboot/+/83271/comment/64991629_b318722a?us… : PS5, Line 49: > The tabs are spurious at this point, please remove. […] Done File src/cpu/intel/model_206ax/model_206ax_init.c: https://review.coreboot.org/c/coreboot/+/83271/comment/9ee319f2_0d6cd461?us… : PS5, Line 180: msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT); : : if (conf->turbo_ratio_limit_1c) { : msr.lo &= ~0xff; : msr.lo |= (conf->turbo_ratio_limit_1c); : } : : if (conf->turbo_ratio_limit_2c) { : msr.lo &= ~(0xff << 8); : msr.lo |= (conf->turbo_ratio_limit_2c << 8); : } : : if (conf->turbo_ratio_limit_3c) { : msr.lo &= ~(0xff << 16); : msr.lo |= (conf->turbo_ratio_limit_3c << 16); : } : : if (conf->turbo_ratio_limit_4c) { : msr.lo &= ~(0xff << 24); : msr.lo |= (conf->turbo_ratio_limit_4c << 24); : } : : wrmsr(MSR_TURBO_RATIO_LIMIT, msr); > nit: drop one tab […] Done https://review.coreboot.org/c/coreboot/+/83271/comment/c210fdd4_10a42574?us… : PS5, Line 333: BIOS_NOTICE > It's expected to be like this on most processors, isn't it? Then it should […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad Gerrit-Change-Number: 83271 Gerrit-PatchSet: 6 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jul 2024 09:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow package power limit clamping
by Nico Huber (Code Review) 15 Jul '24

15 Jul '24

Attention is currently required from: Anastasios Koutian, Angel Pons. Nico Huber has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83270?usp=email ) Change subject: cpu/intel/model_206ax: Allow package power limit clamping ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83270/comment/0ea0e615_f48049ef?us… : PS5, Line 8: > > "Package Clamping Limitation #1 (bit 16): Allow going below OS-requested P/T state setting during […] Hmmm, that wasn't very accurate. More technically: The enable bit makes to go down to the highest non-turbo state if necessary. And the clamping bit makes it to go below that if necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/83270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be Gerrit-Change-Number: 83270 Gerrit-PatchSet: 5 Gerrit-Owner: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasios Koutian <akoutian2(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Jul 2024 09:55:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasios Koutian <akoutian2(a)gmail.com>

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