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Hello Nico Huber, build bot (Jenkins),
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Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
......................................................................
cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
Tested on ThinkPad T420 with the i7-3940XM.
Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad
Signed-off-by: Anastasios Koutian <akoutian2(a)gmail.com>
---
M src/cpu/intel/model_206ax/chip.h
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83271/6
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: cpu/intel/model_206ax: Allow package power limit clamping
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83270/comment/8fb366d5_443347e5?us… :
PS5, Line 8:
> "Package Clamping Limitation #1 (bit 16): Allow going below OS-requested P/T state setting during time window specified by bits 23:17."
> "Package Clamping Limitation #2 (bit 48): Allow going below OS-requested P/T state setting during time window specified by bits 23:17."
It's these vague descriptions that made me ask in the first place. Wouldn't
have asked if it was easy to understand :D With this description and your
tests alone, don't you wonder what the enable bit does vs the clamping bit?
So I looked it up once more: the enable bit tells it to obey the limit in turbo
states. The clamping bit tells it to obey the limit in all states (i.e. also
non-turbo states).
Please put that information into the commit message. That's why I asked here.
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Elyes Haouas has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/83464?usp=email )
Change subject: [IT'S A PAIN - plan to deprecate ?] opensbi submodule
......................................................................
[IT'S A PAIN - plan to deprecate ?] opensbi submodule
Updating from commit id 5019fd1:
2022-09-01 16:53:28 +0530 - (include: sbi: Reduce includes in sbi_pmu.h)
to commit id 0a66754:
2024-07-04 12:11:52 +0530 - (docs: writing tests: update cleaning instructions)
This brings in 540 new commits.
Change-Id: I5f47c3da778908207ee1f41c328b0e933d922c1c
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M 3rdparty/opensbi
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/83464/3
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I'd like you to reexamine a change. Please visit
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Change subject: [IT'S A PAIN - plan to deprecate ?] chromeec submodule
......................................................................
[IT'S A PAIN - plan to deprecate ?] chromeec submodule
Updating from commit id e486b388a7:
2022-01-12 21:11:11 +0000 - (zephyr: Update power policy for API change)
to commit id 410749e609:
2024-07-15 06:48:40 +0000 - (bujia: Remove the unused i2c channel to unused pin)
This brings in 13785 new commits.
Change-Id: I534208aa0c628efe69b1ba14889d76511fd3bc3d
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M 3rdparty/chromeec
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/83466/3
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Change subject: 3rdparty: Remove chromeec submodule
......................................................................
Patch Set 5: Code-Review+1
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Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83355?usp=email )
Change subject: superio/ite/common: Add common driver for GPIO and LED configuration
......................................................................
Patch Set 1:
(5 comments)
File src/mainboard/samsung/stumpy/smihandler.c:
https://review.coreboot.org/c/coreboot/+/83355/comment/746c6919_706f6218?us… :
PS1, Line 25: ite_reg_write(GPIO_DEV, IT8772F_GPIO_REG_SELECT(3), 0x20);
> Now that these are seperate steps, the redundancy becomes obvious: We already […]
Yes, setup_sio_gpios already does it and further writes should not be necessary.
https://review.coreboot.org/c/coreboot/+/83355/comment/3d7d2f3b_843128ee?us… :
PS1, Line 49: ITE_LED_FREQ_1HZ);
> This looks very odd now, configuring blink when it's not used? Traced […]
Right, enabling SIMPLE_IO_MODE in the ite_gpio_setup call should already disable the LED blinking function.
File src/superio/ite/common/gpio.c:
https://review.coreboot.org/c/coreboot/+/83355/comment/f8deb2d6_8f710df7?us… :
PS1, Line 130: */
> It looks like IT8718F doesn't have pull-up set 2? […]
Right, I will revisit these datasheets and fix
File src/superio/ite/it8772f/it8772f.h:
https://review.coreboot.org/c/coreboot/+/83355/comment/abe24211_64d4e3d7?us… :
PS1, Line 16:
: /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */
: #define IT8772F_GPIO_REG_POLARITY(x) (0xb0 + (x))
:
: /* GPIO Internal Pull-up: 1: Enable, 0: Disable */
: #define IT8772F_GPIO_REG_PULLUP(x) (0xb8 + (x))
:
: /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */
: #define IT8772F_GPIO_REG_ENABLE(x) (0xc0 + (x))
:
: /* GPIO Mode: 0: input mode, 1: output mode */
: #define IT8772F_GPIO_REG_OUTPUT(x) (0xc8 + (x))
:
> Why keep them?
Forgot to leave IT8772F_GPIO_REG_SELECT only. But actually all ITE SIOs have these GPIO function selects starting at 0x25, so I will put it into superio/ite/common/ite_gpio.h
File src/superio/ite/it8786e/Kconfig:
https://review.coreboot.org/c/coreboot/+/83355/comment/ad4c4233_8f5ac068?us… :
PS1, Line 16: default 10
> I only see 8?
In the "IT8786E-I Preliminary SPecification v0.4.1 for D version"
section 8.10.10 there is a table of GPIO registers described for sets of up to 0xA (10).
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Attention is currently required from: Angel Pons, Elyes Haouas, Martin L Roth.
Elyes Haouas has uploaded a new patch set (#5) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/81024?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Code-Review+2 by Elyes Haouas, Verified+1 by build bot (Jenkins)
Change subject: 3rdparty: Remove chromeec submodule
......................................................................
3rdparty: Remove chromeec submodule
The chromeec submodule is the largest submodule being pulled into the
coreboot tree, at over 400MB. The main branch also contains the majority
of these commits, so restricting it to a single branch still fetches
over 350MB.
Because there is only a single mainboard directory that enables the
build of the chromeec codebase by default, most people are fetching this
repo for no reason.
Based on this, we're going to change the way that the chromeec submodule
is used, fetching it the way we currently fetch external payloads. This
gives us 2 large advantages:
1) Only builds that actually need the chromeec repo will pull it down.
2) Each board that wants to build the chromeec codebase can use a
different commit, unlike submodules which all use the same "current"
commit.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I357c4c9b506dd3817a308232446144ae889bc220
---
M .gitmodules
D 3rdparty/chromeec
2 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81024/5
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Change subject: mb/google/dedede/var/awasuki: Generate 3 RAM IDs
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83427/comment/b85577bd_7c334d14?us… :
PS5, Line 7: variants
> var , still not changed.
Done
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Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
......................................................................
Patch Set 9:
(2 comments)
File src/mainboard/protectli/vault_adl_p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/25c02a22_0b678055?us… :
PS7, Line 29: }
> Why inline, though? We can add as many C files as we want. Inline only bloats […]
Created a C file with the beep function
https://review.coreboot.org/c/coreboot/+/80501/comment/a719385d_d4a9cd22?us… :
PS7, Line 51: }
> Haven't touched it yet. Will update it soon with another patch.
Uhh, I didn't realize there is a function to get a processor name already under cpu/x86/name. Used it here.
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Change subject: soc/amd/glinda/include/gpio: update to match hardware
......................................................................
Patch Set 1: Code-Review+2
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