Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83523?usp=email )
Change subject: tgl,adl,rpl mainboards: Drop superfluous cpu_cluster device
......................................................................
tgl,adl,rpl mainboards: Drop superfluous cpu_cluster device
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
M src/mainboard/system76/adl/devicetree.cb
M src/mainboard/system76/rpl/devicetree.cb
M src/mainboard/system76/tgl-h/devicetree.cb
M src/mainboard/system76/tgl-u/devicetree.cb
9 files changed, 0 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/83523/1
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 70a8706..ec60894 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -6,8 +6,6 @@
end
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 932a5c7..fb55da4 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 2437880..bbc428e 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -38,8 +38,6 @@
register "pmc_gpe0_dw2" = "GPP_E"
# Device Tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on
register "ddi_portA_config" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 22f824f..7a3f9fb 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -30,8 +30,6 @@
register "pmc_gpe0_dw2" = "GPP_E"
# Device Tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on
register "ddi_portA_config" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 2b7c4f8..c29d7c9 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -63,8 +63,6 @@
register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
# Actual device tree.
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on end
device ref dptf on end
diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb
index 9a7a149..c73bef2c 100644
--- a/src/mainboard/system76/adl/devicetree.cb
+++ b/src/mainboard/system76/adl/devicetree.cb
@@ -19,8 +19,6 @@
# Thermal
register "tcc_offset" = "8"
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb
index 749ce53..34105fc 100644
--- a/src/mainboard/system76/rpl/devicetree.cb
+++ b/src/mainboard/system76/rpl/devicetree.cb
@@ -23,8 +23,6 @@
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "1"
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb
index 11b85ce..58a4fcf 100644
--- a/src/mainboard/system76/tgl-h/devicetree.cb
+++ b/src/mainboard/system76/tgl-h/devicetree.cb
@@ -77,8 +77,6 @@
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# Actual device tree
- device cpu_cluster 0 on end
-
device domain 0 on
#From CPU EDS(575683)
device ref system_agent on end
diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb
index ae80a32..d7a527a 100644
--- a/src/mainboard/system76/tgl-u/devicetree.cb
+++ b/src/mainboard/system76/tgl-u/devicetree.cb
@@ -65,8 +65,6 @@
register "tcc_offset" = "12"
# Actual device tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
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Change subject: vc/google/chromeos: Add configurable compression for logo file in cbfs
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83420/comment/23322dbd_1f06dc37?us… :
PS5, Line 15: ~760ms
This is too big of savings - almost 1 second. Definitely LZMA decompression or loading an uncompressed file does not take that long. Can you please confirm?
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Change subject: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II
......................................................................
Patch Set 11:
(1 comment)
File src/ec/starlabs/merlin/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/80705/comment/0f607686_ada5b312?us… :
PS10, Line 14: Return (0x00)
> should this change be in this patch?
Good spot, no.
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83522?usp=email )
Change subject: util/liveiso/nixos: Install various extractor tools
......................................................................
util/liveiso/nixos: Install various extractor tools
Firmware files are packaged in various formats and very often some
Windows-only executable is used for unpacking files. These extractors
allow to deal with some of them without having to run the executables.
Change-Id: I1346807508a6baba801c4d5ed0a575b17e06c8d4
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M util/liveiso/nixos/common.nix
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83522/1
diff --git a/util/liveiso/nixos/common.nix b/util/liveiso/nixos/common.nix
index d461976..4c906ca 100644
--- a/util/liveiso/nixos/common.nix
+++ b/util/liveiso/nixos/common.nix
@@ -104,6 +104,7 @@
acpica-tools
btrfs-progs
bzip2
+ cabextract
ccrypt
chipsec
coreboot-utils
@@ -130,6 +131,7 @@
hexdump
htop
i2c-tools
+ innoextract
intel-gpu-tools
inxi
iotools
@@ -169,6 +171,7 @@
tpm2-tools
uefitool
uefitoolPackages.old-engine
+ unshield
unzip
upterm
usbutils
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Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS1:
> This is also the first time when the IOM was not ready before SiliconInit. […]
I was more wondering about details about the bit itself, i.e. to check the
offset. What also would be interesting is how long it's supposed to take.
Anyway, I guess we're good. Maybe two more things you could add to the
commit message or the comment for the Protectli:
* How long the polling takes during a cold boot.
* If it's necessary on the resume path too (just out of curiosity).
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Change subject: azalia: Get rid of "return {-1,0}
......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83503/comment/983bc493_c53f6f93?us… :
PS2, Line 9: Modern C uses {true,false}
No. Please see https://doc.coreboot.org/contributing/coding_style.html#function-return-val…
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Change subject: mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II
......................................................................
Patch Set 10:
(1 comment)
File src/ec/starlabs/merlin/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/80705/comment/b7d9ddde_bb7908bb?us… :
PS10, Line 14: Return (0x00)
should this change be in this patch?
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Change subject: mb/starlabs/starlite_adl: Add Alder Lake N StarLite Mk V
......................................................................
Patch Set 10: Code-Review+2
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Change subject: security/vboot: Introduce vbnv_platform_init_cmos()
......................................................................
Patch Set 3: Code-Review+2
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
......................................................................
Patch Set 1:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/83506/comment/2072e6b9_67171717?us… :
PS1, Line 3180: #define PCI_DID_INTEL_PTL_H_ESPI_9 0xe409
> > Hi Subrata, is it required to push 8-31 eSPI IDs for U & H? […]
What I described in https://review.coreboot.org/c/coreboot/+/83506/comment/ef041abf_b118bd01/ would avoid the problem as well
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