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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/12988499_309c3af9?us… :
PS4, Line 16: cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);
Is there any harm in calling cmos_init(0) just like how it is done in ramstage during every boot. cmos_init does this along with other things including detecting the power failure, restoring from the flash backup etc.
If there are no power failures like the one this CL is trying to address, cmos_init just selects the bank and moves on.
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Change subject: superio/ite,mb: Switch to new ITE GPIO driver
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Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83469/comment/76b1b64a_37c6b176?us… :
PS2, Line 11:
> I guess people having the modified boards could build new ROMs and suspend them to S3 to check if th […]
I can test on beltino and jecht; I have a stumpy as well but the power LED has been dead for some time
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
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Patch Set 1:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/83506/comment/1da4aaaa_aff79c04?us… :
PS1, Line 3180: #define PCI_DID_INTEL_PTL_H_ESPI_9 0xe409
> Hi Subrata, is it required to push 8-31 eSPI IDs for U & H?
I followed the instructions in the EDS, but based on my experience, it's always better to cover the entire spectrum. I've seen issues pop up during the factory process in the past, so it's better to be safe and add all the necessary macros.
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
......................................................................
Patch Set 1:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/83506/comment/f72959af_d2635f1a?us… :
PS1, Line 3180: #define PCI_DID_INTEL_PTL_H_ESPI_9 0xe409
Hi Subrata, is it required to push 8-31 eSPI IDs for U & H?
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Change subject: mb/google/brya/var/xol: Limit power limits for low/no battery case
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Patch Set 7: Code-Review+1
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Change subject: device/pci_ids: Add new Intel PTL device IDs for UARTx
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Patch Set 2: Code-Review+2
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Change subject: device/pci_ids: Add new Intel PTL device IDs for CNVi
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Patch Set 2: Code-Review+2
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Change subject: device/pci_ids: Remove unused Intel UFS device IDs
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83519/comment/918a6c24_f8979dd1?us… :
PS1, Line 10: devices from `pci_ids.h` as they appear to be unused in the codebase.
> > I know UFS on ADL is "meh": IIRC, it's only POR on some OSes (Linux, but not Windows). […]
Ack, thanks for the explanation!
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