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Change subject: device/pci_ids: Remove unused Intel UFS device IDs
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83519/comment/f2d61c97_372f24f7?us… :
PS1, Line 10: devices from `pci_ids.h` as they appear to be unused in the codebase.
> I know UFS on ADL is "meh": IIRC, it's only POR on some OSes (Linux, but not Windows). Do you know if things have changed w.r.t. UFS and POR?
good question, bt I can only comment for CrOS where UFS is POR but the UFS communication is only limited to payload. Additionally, we don't have any PCI driver need for UFS in coreboot hence those PCI IDs for UFS may not relevant for us.
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Change subject: soc/intel: Add Panther Lake PCIE device IDs
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
> Hi Subrata, it seems you missed to review the CL before it got merged,
I was waiting to review the once I have access to the doc and I'm doing the review now because I got access to all PTL doc this week early. IMO, the cl landed in rush w/o following the review in proper. For example: we landed LNL DID2 in form of PTL DID2 (details https://review.coreboot.org/c/coreboot/+/83491/1/src/include/device/pci_ids…). Hence, added this section to share my official feedback.
> since during the review, it was asked to remove the SKU Type due to program being in early stage(PSS) and some NDA terms. Following the review comments, SKU Type has been removed,
I don't know which SKU type you are referring here. Atleast I'm only interested to land the SKU IDs that CrOS will build for PTL (and rest can be assumed upsteam late by community)
> though it is planned to update and add SKU U & H info post apporval. Thanks for taking up and pushing the changes required CLs "fatcat_ptl_pci_ids".
I'm not aware of any approval process to be honest here. I got the doc and found that the DIDs are not aligned with our SOC roadmap for PTL hence, I have started by myself knowing you folks have more important work at this stage.
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/68112?usp=email )
Change subject: gma: Work around GNATprove issue with nested loops
......................................................................
gma: Work around GNATprove issue with nested loops
Add some explicit `Loop_Invariant (True)` to work around
odd check messages. These show up since about the spark-
community-2019 release and still with newer versions,
which almost seem to hang (takes some minutes longer than
expected). Example messages are provided below. Given that
the values are in the ranges as stated by the `for` loops,
they can't be out of range.
hw-gfx-gma-plls.adb:323:14: medium: range check might fail
323 | for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
| ^~
hw-gfx-gma-plls.adb:325:17: medium: range check might fail
325 | for M2 in reverse M2_Range range Limits.M2_Lower .. Int64'Min (Limits.M2_Upper, M1)
| ^~
hw-gfx-gma-plls.adb:327:20: medium: range check might fail
327 | for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
| ^~
hw-gfx-gma-plls.adb:332:41: medium: range check might fail
332 | M2 => M2,
| ^~
reason for check: input value must fit in parameter type
Change-Id: I5430081767c760b85401300e0db4d26fd78270d7
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/68112
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M common/g45/hw-gfx-gma-plls.adb
M common/ironlake/hw-gfx-gma-plls.adb
2 files changed, 4 insertions(+), 0 deletions(-)
Approvals:
Nico Huber: Verified
Angel Pons: Looks good to me, approved
diff --git a/common/g45/hw-gfx-gma-plls.adb b/common/g45/hw-gfx-gma-plls.adb
index 67242f2..5db76d6 100644
--- a/common/g45/hw-gfx-gma-plls.adb
+++ b/common/g45/hw-gfx-gma-plls.adb
@@ -322,8 +322,10 @@
-- reverse loops as hardware prefers higher values
for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
loop
+ pragma Loop_Invariant (True);
for M2 in reverse M2_Range range Limits.M2_Lower .. Int64'Min (Limits.M2_Upper, M1)
loop
+ pragma Loop_Invariant (True);
for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
loop
Verify_Parameters
diff --git a/common/ironlake/hw-gfx-gma-plls.adb b/common/ironlake/hw-gfx-gma-plls.adb
index 10e9ff2..8b6ca36 100644
--- a/common/ironlake/hw-gfx-gma-plls.adb
+++ b/common/ironlake/hw-gfx-gma-plls.adb
@@ -291,8 +291,10 @@
-- reverse loops as hardware prefers higher values
for M1 in reverse M1_Range range Limits.M1_Lower .. Limits.M1_Upper
loop
+ pragma Loop_Invariant (True);
for M2 in reverse M2_Range range Limits.M2_Lower .. Limits.M2_Upper
loop
+ pragma Loop_Invariant (True);
for P1 in reverse P1_Range range Limits.P1_Lower .. Limits.P1_Upper
loop
Verify_Parameters
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Change subject: gma: Work around GNATprove issue with nested loops
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Patch Set 3: Verified+1
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Change subject: soc/intel: Add Panther Lake PCIE device IDs
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
> Thanks for letting me know.
Hi Subrata, it seems you missed to review the CL before it got merged, since during the review, it was asked to remove the SKU Type due to program being in early stage(PSS) and some NDA terms. Following the review comments, SKU Type has been removed, though it is planned to update and add SKU U & H info post apporval. Thanks for taking up and pushing the changes required CLs "fatcat_ptl_pci_ids".
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Change subject: mb/google/dedede: Create awasuki variant
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Patch Set 15: Code-Review+2
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Change subject: mb/google/dedede: Create awasuki variant
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Patch Set 15: Code-Review+1
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
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Patch Set 5: Code-Review+1
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