Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83493?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brya: Standardize TPM TIS ACPI interrupt configuration
......................................................................
mb/google/brya: Standardize TPM TIS ACPI interrupt configuration
This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for
the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google
Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/
GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/
GPP_A17_IRQ).
This refactoring simplifies future additions of board-specific TPM
interrupt configurations, improving maintainability.
BUG=none
TEST=The timeless builds with this patch for both Nissa and Brya
devices produce the same binaries.
Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 59 insertions(+), 2 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index e235fec..10ae55f 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -724,9 +724,66 @@
config TPM_TIS_ACPI_INTERRUPT
int
+ default 13 if BOARD_GOOGLE_AGAH # GPE0_DW0_13 (GPP_A13_IRQ)
+ default 13 if BOARD_GOOGLE_ANAHERA
+ default 13 if BOARD_GOOGLE_ANAHERA4ES
+ default 13 if BOARD_GOOGLE_ANRAGGAR
+ default 13 if BOARD_GOOGLE_AURASH
+ default 13 if BOARD_GOOGLE_BANSHEE
+ default 13 if BOARD_GOOGLE_BRASK
+ default 13 if BOARD_GOOGLE_BRYA0
+ default 13 if BOARD_GOOGLE_BUJIA
+ default 13 if BOARD_GOOGLE_CONSTITUTION
+ default 13 if BOARD_GOOGLE_CRAASK
+ default 13 if BOARD_GOOGLE_CRAASKOV
+ default 13 if BOARD_GOOGLE_CROTA
+ default 13 if BOARD_GOOGLE_DOCHI
+ default 13 if BOARD_GOOGLE_DOMIKA
+ default 13 if BOARD_GOOGLE_FELWINTER
+ default 13 if BOARD_GOOGLE_GAELIN
+ default 13 if BOARD_GOOGLE_GIMBLE
+ default 13 if BOARD_GOOGLE_GIMBLE4ES
+ default 13 if BOARD_GOOGLE_GLADIOS
+ default 13 if BOARD_GOOGLE_GLASSWAY
+ default 13 if BOARD_GOOGLE_GOTHRAX
+ default 20 if BOARD_GOOGLE_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
+ default 13 if BOARD_GOOGLE_JOXER
+ default 13 if BOARD_GOOGLE_KANO
+ default 13 if BOARD_GOOGLE_KINOX
+ default 13 if BOARD_GOOGLE_KULDAX
+ default 13 if BOARD_GOOGLE_LISBON
+ default 13 if BOARD_GOOGLE_MARASOV
+ default 13 if BOARD_GOOGLE_MITHRAX
+ default 13 if BOARD_GOOGLE_MOLI
+ default 13 if BOARD_GOOGLE_NEREID
+ default 13 if BOARD_GOOGLE_NIVVIKS
+ default 13 if BOARD_GOOGLE_NOVA
+ default 13 if BOARD_GOOGLE_OMNIGUL
default 17 if BOARD_GOOGLE_ORISA # GPE0_DW0_17 (GPP_A17_IRQ)
- default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
- default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ)
+ default 13 if BOARD_GOOGLE_OSIRIS
+ default 13 if BOARD_GOOGLE_PIRRHA
+ default 13 if BOARD_GOOGLE_PRIMUS
+ default 13 if BOARD_GOOGLE_PUJJO
+ default 13 if BOARD_GOOGLE_QUANDISO
+ default 13 if BOARD_GOOGLE_REDRIX
+ default 13 if BOARD_GOOGLE_REDRIX4ES
+ default 13 if BOARD_GOOGLE_RIVEN
+ default 13 if BOARD_GOOGLE_SKOLAS
+ default 13 if BOARD_GOOGLE_SKOLAS4ES
+ default 13 if BOARD_GOOGLE_TAEKO
+ default 13 if BOARD_GOOGLE_TAEKO4ES
+ default 13 if BOARD_GOOGLE_TANIKS
+ default 13 if BOARD_GOOGLE_TEREID
+ default 13 if BOARD_GOOGLE_TIVVIKS
+ default 13 if BOARD_GOOGLE_TRULO
+ default 13 if BOARD_GOOGLE_ULDREN
+ default 13 if BOARD_GOOGLE_VELL
+ default 13 if BOARD_GOOGLE_VOLMAR
+ default 13 if BOARD_GOOGLE_XIVU
+ default 13 if BOARD_GOOGLE_XOL
+ default 13 if BOARD_GOOGLE_YAVIKS
+ default 13 if BOARD_GOOGLE_YAVILLA
+ default 13 if BOARD_GOOGLE_ZYDRON
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
......................................................................
Patch Set 1:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/83506/comment/99fd2e77_ff51076e?us… :
PS1, Line 3180: #define PCI_DID_INTEL_PTL_H_ESPI_9 0xe409
> > What I described in https://review.coreboot.org/c/coreboot/+/83506/comment/ef041abf_b118bd01/ would avoid the problem as well
>
> I have shared some thoughts there as well why we eventually need to describe all support PCH IDs
marking resolved based on other thread part of same CL.
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Subrata Banik has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/83346?usp=email )
Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Please refer to the bug for the detail. Add Jamie@intel for any further question.
>
> - We can refer to this comment for why we have IOAPIC configuration has this problem.: https://partnerissuetracker.corp.google.com/issues/350609957#comment22. I just assume GPI_INT has differt mechanism to handle its interrupt status in SoC or GPIO driver, Intel can help for any comment about it.
if SoC is using same IRQ number for its internal device then changing this PIN to GPI IOAPIC makes lot more sense to me but looks like other parts are happily using same PIN for IOAPIC hence, I'm suspecting some abnormality with the device firmware.
I don't know the timing difference between IOAPIC interrupt vs GPI IOAPIC interrupt.
>
> - We had discussion with device vendor in the bug, they said cannot change interrupt signal timing in device firmware.: https://partnerissuetracker.corp.google.com/issues/350609957#comment27
if device firmware acknowledge there is some limitation hence, we should be good to support this CL.
Do you know if the device fw is meeting Intel's minimum IRQ width (150uS) requirement for ADL
>
> - We had 2 options for this problem, one was a patch in kernel side and another one was this patch. And we choose this change for Xol.
>
> - Actually we didn't try Edge Single interrupt configuration but I think it may cause DUT to miss interrupts from device on continuous user input on touchpad.
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/83506/comment/abb14287_1473731f?us… :
PS1, Line 143: static const unsigned short pci_device_ids[] = {
> Yeah, we'd still need the IDs there. Fortunately, `report_platform.c` is SoC-specific, so the lists are not as long. It's also non-critical to function, so it would only impact the log output (which most non-developers won't see anyway).
>
> The main idea is to avoid having to potentially iterate over 300 IDs (worst-case) to try binding the ops to a device we always know is at PCI B:D.F `00:1f.0`.
I would still like to keep this check as the PCI device ID check is a crucial mechanism in Linux to ensure the correct, safe, and efficient operation of a wide range of hardware devices. Skipping the check would introduce significant risks and limitations, undermining the stability and functionality of the system.
for example: knowingly or unknowingly ppl can try to bind other device to LPC/eSPI driver results into mismatched drivers or incorrect resource allocation can lead to system instability, crashes, or even security vulnerabilities.
coming to the data, 300 device id check for Intel latest SoC would take 207 microseconds roughly.
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Change subject: device/pci_ids: Add new Intel PTL device IDs for eSPI/LPC
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/83506/comment/fa01d886_219ce89a?us… :
PS1, Line 143: static const unsigned short pci_device_ids[] = {
> > For another patch: bind the LPC/eSPI ops through the chipset devicetree instead of having such a l […]
Yeah, we'd still need the IDs there. Fortunately, `report_platform.c` is SoC-specific, so the lists are not as long. It's also non-critical to function, so it would only impact the log output (which most non-developers won't see anyway).
The main idea is to avoid having to potentially iterate over 300 IDs (worst-case) to try binding the ops to a device we always know is at PCI B:D.F `00:1f.0`.
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> we might need to dig deep to find out why the behavior is not identical with other Brya platform tha […]
Please refer to the bug for the detail. Add Jamie@intel for any further question.
- We can refer to this comment for why we have IOAPIC configuration has this problem.: https://partnerissuetracker.corp.google.com/issues/350609957#comment22. I just assume GPI_INT has differt mechanism to handle its interrupt status in SoC or GPIO driver, Intel can help for any comment about it.
- We had discussion with device vendor in the bug, they said cannot change interrupt signal timing in device firmware.: https://partnerissuetracker.corp.google.com/issues/350609957#comment27
- We had 2 options for this problem, one was a patch in kernel side and another one was this patch. And we choose this change for Xol.
- Actually we didn't try Edge Single interrupt configuration but I think it may cause DUT to miss interrupts from device on continuous user input on touchpad.
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
we might need to dig deep to find out why the behavior is not identical with other Brya platform that also uses GPP_F14 for Touch as IOAPIC Interrupt. Looks like in your case the only working combination is by making it act as GPI IOxAPIC interrupt. GPI IOxAPIC routed via a GPIO mux hence, i would always prefer to have a dedicated IOAPIC interrupt like other Brya design.
can you please start looking part vendor to understand this issue from device side as well. If there is any overflow of the packet while device FW unable to handle where else changing this to GPI IOxAPIC interrupt reduces the number of IRQ.
Btw, have you tried to change the configuration from LEVEL to Edge Single ?
```
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, EDGE_SINGLE, INVERT),
```
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
Patch Set 5: -Code-Review
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83496/comment/8f950620_08386bee?us… :
PS5, Line 12: google/brya -b anraggar
google/dedede -b awasuki
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Hello Karthik Ramasubramanian, Shelley Chen, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83420?usp=email
to look at the new patch set (#6).
Change subject: vc/google/chromeos: Add configurable compression for logo file in cbfs
......................................................................
vc/google/chromeos: Add configurable compression for logo file in cbfs
This patch enables LZMA or LZ4 compression algorithm for the logo cbfs
file based on BMP_LOGO_COMPRESS_LZMA or BMP_LOGO_COMPRESS_LZ4 Kconfig.
Logo cbfs file is compressed based on CBFS_COMPRESS_FLAG, by default.
Based on logo file content and target platform, enabling LZ4 could
save significant boot time, with increase in file size.
For brox:
cb_logo LZ4 is +1265 bytes than LZMA, saves ~0.760ms in decomp.
cb_plus_logo LZ4 is +2011 bytes than LZMA, saves ~0.880ms in decomp.
BUG=b:337330958
TEST=Able to boot brox and verified firmware splash screen display
with LZMA and LZ4 compression.
Change-Id: I57fbd0d3a39eaba3fb9d61e7a3fb5eeb44e3a839
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/vendorcode/google/chromeos/Makefile.mk
1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/83420/6
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Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I57fbd0d3a39eaba3fb9d61e7a3fb5eeb44e3a839
Gerrit-Change-Number: 83420
Gerrit-PatchSet: 6
Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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