Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83539?usp=email )
Change subject: mb/google/brya/var/trulo: Add Lp5 DRAM (MT62F512M32D2DR-031)
......................................................................
mb/google/brya/var/trulo: Add Lp5 DRAM (MT62F512M32D2DR-031)
This patch adds LPDDR5 DRAM (part: MT62F512M32D2DR-031) for Trulo.
Make use of spd_tools to generate SPD file after following the below
steps:
1. make -C util/spd_tools
2. ./util/spd_tools/bin/part_id_gen ADL lp5
src/mainboard/google/brya/variants/trulo/memory
src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
Output files are:
1. dram_id.generated.txt
2. Makefile.mk
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Id35f6b57b716375abb66db187413f0f82361d962
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/memory/Makefile.mk
M src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
3 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/83539/1
diff --git a/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk b/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk
index 850a62c..5cb4476 100644
--- a/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/trulo/memory/Makefile.mk
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# /tmp/go-build204585115/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B
diff --git a/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt
index 8ce2480..8790f22 100644
--- a/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/trulo/memory/dram_id.generated.txt
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# /tmp/go-build204585115/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
+# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/trulo/memory src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
DRAM Part Name ID to assign
+MT62F512M32D2DR-031 WT:B 0 (0000)
diff --git a/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
index 2499005..fc41c85 100644
--- a/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
@@ -9,3 +9,4 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+MT62F512M32D2DR-031 WT:B
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83496/comment/58d1dbd8_0da67adf?us… :
PS5, Line 12: google/brya -b anraggar
> google/dedede -b awasuki
Done
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Change subject: mb/google/dedede/var/awasuki: Initialise overridetree
......................................................................
mb/google/dedede/var/awasuki: Initialise overridetree
Initialise overridetree based on the schematics revision 20240715.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ie8194b6eca3e88f08f92e0ac8a9063b8de738652
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/variants/awasuki/Makefile.mk
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
A src/mainboard/google/dedede/variants/awasuki/ramstage.c
4 files changed, 208 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83496/6
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/05689beb_e8194b6b?us… :
PS4, Line 16: cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);
> calling cmos_init(0) just like how it is done in ramstage during every boot
That sounds fine, if intel is doing the same (calling cmos_init in RO). Done.
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Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
......................................................................
drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] lore.kernel.org/lkml/20220523165815.913462426@linuxfoundation.org
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/drivers/pc80/rtc/mc146818rtc.c
M src/include/pc80/mc146818rtc.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/83537/1
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index 6474ecb..c44bfd3 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -65,6 +65,9 @@
#define RTC_CONTROL_DEFAULT (RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
+_Static_assert(!CONFIG(SOC_AMD_COMMON) || !(RTC_FREQ_SELECT_AMD & RTC_AMD_BANK_SELECT),
+ "Bank 1 should not be selected for AMD");
+
static bool __cmos_init(bool invalid)
{
bool cmos_invalid;
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 7818421..701cc73 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -33,6 +33,8 @@
# define RTC_REF_CLCK_4MHZ 0x00
# define RTC_REF_CLCK_1MHZ 0x10
# define RTC_REF_CLCK_32KHZ 0x20
+ /* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */
+# define RTC_AMD_BANK_SELECT 0x10
/* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
In AMD platforms, the bit 4 of CMOS's Register A (0x0a) is DV0 bank
selection (0 for Bank 0; 1 for Bank 1) [1]. Since the MC146818 driver
accesses VBNV via Bank 0, the bit must be cleared before we can save
VBNV to CMOS in verstage.
Usually there's no problem with that, because the Register A is
configured in cmos_init() in ramstage. However, if CMOS has lost power,
then in the first boot after that, the bit may contain arbitrary data in
verstage. If that bit happens to be 1, then CMOS writes in verstage will
fail.
To fix the problem, define vbnv_platform_init_cmos() to call
cmos_init(0), which will configure the Register A and therefore allow
saving VBNV to CMOS in verstage.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=CMOS writes succeeded in verstage after battery cutoff
BRANCH=skyrim
Change-Id: Idf167387b403be1977ebc08daa1f40646dd8c83f
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/amd/common/vboot/vbnv_cmos.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83495/5
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83489?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/meteorlake: Remove p2sb.c from bootblock build
......................................................................
soc/intel/meteorlake: Remove p2sb.c from bootblock build
This patch removes `p2sb.c` from the bootblock build for the
Meteor Lake platform.
BUG=none
TEST=Builds successfully for google/rex.
Change-Id: Ib2beeee68bb20568888d4b555c2fa82e0bf0fd3c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83489
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/soc/intel/meteorlake/Makefile.mk
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk
index 893523c..72d1117 100644
--- a/src/soc/intel/meteorlake/Makefile.mk
+++ b/src/soc/intel/meteorlake/Makefile.mk
@@ -18,7 +18,6 @@
bootblock-y += bootblock/report_platform.c
bootblock-y += bootblock/soc_die.c
bootblock-y += espi.c
-bootblock-y += p2sb.c
bootblock-y += soc_info.c
romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
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