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Change subject: soc/intel/meteorlake: Incrase CAR STACK_SIZE by 31KB to meet coreboot requirements
......................................................................
soc/intel/meteorlake: Incrase CAR STACK_SIZE by 31KB to meet coreboot requirements
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
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BUG=None
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Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83540/4
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Change subject: mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant
......................................................................
Patch Set 1: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/meteorlake: Incrase CAR STACK_SIZE by 31KB to meet coreboot requirements
......................................................................
soc/intel/meteorlake: Incrase CAR STACK_SIZE by 31KB to meet coreboot requirements
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
TEST=None
Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: rishikraj <rishikaraj(a)google.com>
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83540/3
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Change subject: mb/google/brya/var/trulo: Populate DRAM configuration parameters
......................................................................
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Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Rishika Raj, Subrata Banik, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Julius Werner, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83540?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Incrase CAR STACK_SIZE to meet coreboot requirements
......................................................................
soc/intel/meteorlake: Incrase CAR STACK_SIZE to meet coreboot requirements
This change increases the DCACHE_BSP_STACK_SIZE from 512KB + 1KB to
512KB + 32KB, addressing a requirement specified by coreboot where
stack usage is higher than 1KB alone.
BUG=None
TEST=None
Change-Id: Iba3620b3b7c470176330f5e07989cd3f6238713e
Signed-off-by: rishikraj <rishikaraj(a)google.com>
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83540/2
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Change subject: mb/google/brya/var/trulo: Add Lp5 DRAM (MT62F512M32D2DR-031)
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant
......................................................................
mb/google/brya: Enable SKIP_RAM_ID_STRAPS for TRULO variant
This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as
this board design won't stuff MEM strap GPIO hence, sets the static
SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/trulo/memory.c
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/83543/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 95107c9..a5bae12 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -550,6 +550,7 @@
config BOARD_GOOGLE_TRULO
select BOARD_GOOGLE_BASEBOARD_TRULO
+ select SKIP_RAM_ID_STRAPS
select SOC_INTEL_TWINLAKE
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
@@ -1000,4 +1001,16 @@
int
default 33
+config SKIP_RAM_ID_STRAPS
+ bool
+ default n
+ help
+ Enable this option if the board variant does not rely on MEM Strap GPIOs to determine the SPD ID.
+
+ This is typically the case when the DRAM part is fixed (only one type is used).
+ In such board designs, enabling this option will bypass the reading of MEM Strap GPIOs
+ and instead use a static SPD ID number.
+
+ If unsure, leave this option disabled.
+
endif # BOARD_GOOGLE_BRYA_COMMON
diff --git a/src/mainboard/google/brya/variants/trulo/memory.c b/src/mainboard/google/brya/variants/trulo/memory.c
index a6f16db..062854e 100644
--- a/src/mainboard/google/brya/variants/trulo/memory.c
+++ b/src/mainboard/google/brya/variants/trulo/memory.c
@@ -76,6 +76,9 @@
int variant_memory_sku(void)
{
+ if (CONFIG(SKIP_RAM_ID_STRAPS))
+ return 0; /* SPD ID: 0 - MT62F512M32D2DR-031 WT:B */
+
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E2
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