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Change subject: mb/google/brya/var/trulo: Add Lp5 DRAM (MT62F512M32D2DR-031)
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83539/comment/251e8969_45bbf11f?us… :
PS1, Line 7: Lp5 DRAM
This spelling does not have any hits on the Web for me. Use LPDDR5?
https://review.coreboot.org/c/coreboot/+/83539/comment/0b35ab93_0bd55078?us… :
PS1, Line 9: MT
Note to self: That is Micron Technology
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Change subject: ec/system76/ec: Remove RPM calculation
......................................................................
ec/system76/ec: Remove RPM calculation
System76 EC since system76/ec@80cfa91b9fd5 ("acpi: Report RPM values
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 5: Code-Review+2
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: ec/system76/ec: Remove RPM calculation
......................................................................
ec/system76/ec: Remove RPM calculation
System76 EC since system76/ec@80cfa91b9fd5 ("acpi: Report RPM values
instead of raw tachometer values") performs the RPM calculation itself
and stores it in EC RAM where previously the raw tachometer values were
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Ref: https://github.com/system76/ec/pull/456
Change-Id: I82a4e25a8ce0f274b2d98e7ff2b12595acf6c3c5
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---
M src/ec/system76/ec/acpi/s76.asl
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83308/2
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> > > Please refer to the bug for the detail. Add Jamie@intel for any further question. […]
Updated commit message and added FIXME into the code to mark that we're now investigating and would change back the interrupt type to IRQxAPIC if possible like other brya variants.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
I have made some changes to migrate some headers/APIs into common code to ease the PTL development. Please leverage those while rebasing this CL.
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Change subject: superio/ite,mb: Switch to new ITE GPIO driver
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83469/comment/5e8ffd22_a1e0d161?us… :
PS2, Line 11:
> Do you mind me adding Tested-By to the commit message?
not at all, please do
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Change subject: superio/ite,mb: Switch to new ITE GPIO driver
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83469/comment/11eb28e4_9ee4ed03?us… :
PS2, Line 11:
> verified working on jecht; couldn't test beltino since the panther variant I have doesn't support LE […]
Do you mind me adding Tested-By to the commit message?
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Change subject: mb/google/brya/var/trulo: Add minimal devicetree entries to boot
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/var/trulo: Add minimal devicetree entries to boot
......................................................................
mb/google/brya/var/trulo: Add minimal devicetree entries to boot
This patch adds minimal device entries and chip configs for Trulo
overridetree.cb to boot.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83546/1
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 9285c33..9fba6ae 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -1,8 +1,32 @@
chip soc/intel/alderlake
+ register "sagv" = "SaGv_Enabled"
+
+ # GPE configuration
+ register "pmc_gpe0_dw1" = "GPP_B"
+ register "pmc_gpe0_dw2" = "GPP_F"
+
+ # S0ix enable
+ register "s0ix_enable" = "1"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
- device domain 0 on
- end
+ device domain 0 on
+ device ref igpu on end
+ device ref shared_sram on end
+ device ref heci1 on end
+ device ref emmc on end
+ device ref ish on
+ chip drivers/intel/ish
+ register "add_acpi_dma_property" = "true"
+ device generic 0 on end
+ end
+ end
+ device ref ufs on end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
+ end
end
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