Attention is currently required from: Arthur Heymans.
Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83559?usp=email )
Change subject: Makefile.inc: Remove linker warning on RWX segments
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83559/comment/201034a3_9574018f?us… :
PS1, Line 606: ons
*on*
--
To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4
Gerrit-Change-Number: 83559
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Thu, 18 Jul 2024 20:59:30 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Attention is currently required from: Arthur Heymans, Jérémy Compostella.
Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/83561?usp=email )
Change subject: arch/x86: Link ramstage in one go
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83561/comment/598eeb57_e11859ba?us… :
PS1, Line 10: reason this reduces the size of the binary.
Unused string constants couldn't be garbage collected anymore. Maybe
it's just because the `.o` was linked with the wrong options, though.
File src/arch/x86/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83561/comment/b4a4fc54_27690d16?us… :
PS1, Line 291: LD_MACHINE
was only used below, can be dropped
--
To view, visit https://review.coreboot.org/c/coreboot/+/83561?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib5848ed44c94780acee1cf900f58162256f3c6da
Gerrit-Change-Number: 83561
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Thu, 18 Jul 2024 20:56:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Jérémy Compostella.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83561?usp=email )
Change subject: arch/x86: Link ramstage in one go
......................................................................
arch/x86: Link ramstage in one go
Link ramstage in one go instead of doing partial linking. For some
reason this reduces the size of the binary.
Qemu i440fx:
before:
fallback/ramstage 65321 LZMA (139572 decompressed)
after
fallback/ramstage 60387 LZMA (124228 decompressed)
Also for LTO to work linking needs to be done in one go.
Change-Id: Ib5848ed44c94780acee1cf900f58162256f3c6da
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.mk
1 file changed, 3 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/83561/1
diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk
index 2bd4338..1a59ee9 100644
--- a/src/arch/x86/Makefile.mk
+++ b/src/arch/x86/Makefile.mk
@@ -315,13 +315,9 @@
$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
cp $< $@
-$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
- @printf " CC $(subst $(obj)/,,$(@))\n"
- $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
-
-$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
- @printf " CC $(subst $(obj)/,,$(@))\n"
- $(LD_ramstage) $(LD_MACHINE) -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
+ @printf " LINK $(subst $(obj)/,,$(@))\n"
+ $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_ramstage) --end-group -T $(call src-to-obj,ramstage,$(CONFIG_MEMLAYOUT_LD_FILE))
endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
--
To view, visit https://review.coreboot.org/c/coreboot/+/83561?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib5848ed44c94780acee1cf900f58162256f3c6da
Gerrit-Change-Number: 83561
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83560?usp=email )
Change subject: Makefile.inc: Mark stack as not executable
......................................................................
Makefile.inc: Mark stack as not executable
Suppress the warning:
missing .note.GNU-stack section implies executable stack
NOTE: This behaviour is deprecated and will be removed in a
future version of the linker
Since we don't need an executable stack this is fine. Some newer
linkers like LLD even default to this.
Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83560/1
diff --git a/Makefile.mk b/Makefile.mk
index 12cd449..4700738 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -603,6 +603,7 @@
LDFLAGS_common += -nostdlib
LDFLAGS_common += --nmagic
LDFLAGS_common += -static
+LDFLAGS_common += -z noexecstack
# Disable warning ons segments with RWX.
# All loadable sections are placed in the same segment for simplicity.
LDFLAGS_common += --no-warn-rwx-segments
--
To view, visit https://review.coreboot.org/c/coreboot/+/83560?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481
Gerrit-Change-Number: 83560
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83559?usp=email )
Change subject: Makefile.inc: Remove linker warning on RWX segments
......................................................................
Makefile.inc: Remove linker warning on RWX segments
Silence a linker warnings about segments with RWX. Having one segment
for all sections is a good design choice as it makes parsing the elf
into a loadable binary simpler.
Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83559/1
diff --git a/Makefile.mk b/Makefile.mk
index b4532c3..12cd449 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -603,6 +603,9 @@
LDFLAGS_common += -nostdlib
LDFLAGS_common += --nmagic
LDFLAGS_common += -static
+# Disable warning ons segments with RWX.
+# All loadable sections are placed in the same segment for simplicity.
+LDFLAGS_common += --no-warn-rwx-segments
# Workaround for RISC-V linker bug, merge back into above line when fixed.
# https://sourceware.org/bugzilla/show_bug.cgi?id=27180
--
To view, visit https://review.coreboot.org/c/coreboot/+/83559?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4
Gerrit-Change-Number: 83559
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj.
Subrata Banik has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83555?usp=email )
Change subject: mb/google/brya/variants/orisa: Remove dummy USB2 Port 10 entry
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/orisa/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83555/comment/79337d4a_707777a5?us… :
PS1, Line 453: chip drivers/usb/acpi
: register "desc" = ""USB2 Bluetooth""
: register "type" = "UPC_TYPE_INTERNAL"
: register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
: device ref usb2_port10 on end
: end
need to delete this as well.
--
To view, visit https://review.coreboot.org/c/coreboot/+/83555?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I355e4cdf70fbbc049d92265b0dee62e1d1545e36
Gerrit-Change-Number: 83555
Gerrit-PatchSet: 1
Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Eric Lai <ericllai(a)google.com>
Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Comment-Date: Thu, 18 Jul 2024 19:15:08 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Rishika Raj has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83555?usp=email )
Change subject: mb/google/brya/variants/orisa: Remove dummy USB2 Port 10 entry
......................................................................
mb/google/brya/variants/orisa: Remove dummy USB2 Port 10 entry
This removes the dummy entry for usb2_ports[9] as it doesn't exist on
the SoC as per USB2 port mapping.
BUG=None
TEST=emerge-nissa coreboot
Change-Id: I355e4cdf70fbbc049d92265b0dee62e1d1545e36
Signed-off-by: Rishika Raj <rishikaraj(a)google.com>
---
M src/mainboard/google/brya/variants/orisa/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/83555/1
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index f04eee2..9843272 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -90,7 +90,6 @@
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
--
To view, visit https://review.coreboot.org/c/coreboot/+/83555?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I355e4cdf70fbbc049d92265b0dee62e1d1545e36
Gerrit-Change-Number: 83555
Gerrit-PatchSet: 1
Gerrit-Owner: Rishika Raj <rishikaraj(a)google.com>