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Change subject: soc/amd/cezanne: Give PSP verstage 4K more space
......................................................................
soc/amd/cezanne: Give PSP verstage 4K more space
To allow CMOS initialization in verstage, the current reserved size 108K
(PSP_SRAM_SIZE - PSP_VERSTAGE_STACK_SIZE = 148K - 40K) is not enough.
Preserve more space for verstage by reducing the stack size by 4K.
Change-Id: I9f53a45d67782d3e425f423d0715a45482b2edea
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/83564/1
diff --git a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
index 569d6e1..ab11448 100644
--- a/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
+++ b/src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
@@ -17,7 +17,7 @@
* and make the size a multiple of 4k
*/
-#define PSP_VERSTAGE_STACK_START 0x41000
-#define PSP_VERSTAGE_STACK_SIZE (40K)
+#define PSP_VERSTAGE_STACK_START 0x42000
+#define PSP_VERSTAGE_STACK_SIZE (36K)
#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */
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Hello Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83537?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Paul Menzel, Verified-1 by build bot (Jenkins)
Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
......................................................................
drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] lore.kernel.org/lkml/20220523165815.913462426@linuxfoundation.org
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/drivers/pc80/rtc/mc146818rtc.c
M src/include/pc80/mc146818rtc.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/83537/2
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Change subject: Makefile.inc: Mark stack as not executable
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83560/comment/fd078d9a_08975a71?us… :
PS2, Line 7: Makefile.inc: Mark stack as not executable
Makefile.mk
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Change subject: Makefile.inc: Remove linker warning on RWX segments
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83559/comment/06d3de90_c53d6a37?us… :
PS2, Line 7: Makefile.inc: Remove linker warning on RWX segments
Makefile.mk
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83523?usp=email )
Change subject: tgl,adl,rpl mainboards: Drop superfluous cpu_cluster device
......................................................................
tgl,adl,rpl mainboards: Drop superfluous cpu_cluster device
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523
Reviewed-by: Tim Crawford <tcrawford(a)system76.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
M src/mainboard/system76/adl/devicetree.cb
M src/mainboard/system76/rpl/devicetree.cb
M src/mainboard/system76/tgl-h/devicetree.cb
M src/mainboard/system76/tgl-u/devicetree.cb
9 files changed, 0 insertions(+), 18 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Crawford: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 70a8706..ec60894 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -6,8 +6,6 @@
end
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 932a5c7..fb55da4 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -1,7 +1,5 @@
chip soc/intel/alderlake
- device cpu_cluster 0 on end
-
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
index 2437880..bbc428e 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
@@ -38,8 +38,6 @@
register "pmc_gpe0_dw2" = "GPP_E"
# Device Tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on
register "ddi_portA_config" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 22f824f..7a3f9fb 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -30,8 +30,6 @@
register "pmc_gpe0_dw2" = "GPP_E"
# Device Tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on
register "ddi_portA_config" = "1"
diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
index 2b7c4f8..c29d7c9 100644
--- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
@@ -63,8 +63,6 @@
register "PcieClkSrcClkReq[6]" = "PCIE_CLK_NOTUSED"
# Actual device tree.
- device cpu_cluster 0 on end
-
device domain 0 on
device ref igpu on end
device ref dptf on end
diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb
index 9a7a149..c73bef2c 100644
--- a/src/mainboard/system76/adl/devicetree.cb
+++ b/src/mainboard/system76/adl/devicetree.cb
@@ -19,8 +19,6 @@
# Thermal
register "tcc_offset" = "8"
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb
index 749ce53..34105fc 100644
--- a/src/mainboard/system76/rpl/devicetree.cb
+++ b/src/mainboard/system76/rpl/devicetree.cb
@@ -23,8 +23,6 @@
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "1"
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb
index 11b85ce..58a4fcf 100644
--- a/src/mainboard/system76/tgl-h/devicetree.cb
+++ b/src/mainboard/system76/tgl-h/devicetree.cb
@@ -77,8 +77,6 @@
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# Actual device tree
- device cpu_cluster 0 on end
-
device domain 0 on
#From CPU EDS(575683)
device ref system_agent on end
diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb
index ae80a32..d7a527a 100644
--- a/src/mainboard/system76/tgl-u/devicetree.cb
+++ b/src/mainboard/system76/tgl-u/devicetree.cb
@@ -65,8 +65,6 @@
register "tcc_offset" = "12"
# Actual device tree
- device cpu_cluster 0 on end
-
device domain 0 on
device ref system_agent on end
device ref igpu on
--
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83536?usp=email )
Change subject: soc/intel/tigerlake: Add cpu_cluster device to PCH-H devicetree
......................................................................
soc/intel/tigerlake: Add cpu_cluster device to PCH-H devicetree
Change-Id: I30a98ae4989edc97d56d2b538930b3c67565d9dc
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83536
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/soc/intel/tigerlake/chipset_pch_h.cb
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Crawford: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chipset_pch_h.cb b/src/soc/intel/tigerlake/chipset_pch_h.cb
index b0eabe9..40f613f 100644
--- a/src/soc/intel/tigerlake/chipset_pch_h.cb
+++ b/src/soc/intel/tigerlake/chipset_pch_h.cb
@@ -1,4 +1,5 @@
chip soc/intel/tigerlake
+ device cpu_cluster 0 on end
device domain 0 on
device gpio 0 alias pch_gpio on end
device pci 00.0 alias system_agent on end
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83522?usp=email )
Change subject: util/liveiso/nixos: Install various extractor tools
......................................................................
util/liveiso/nixos: Install various extractor tools
Firmware files are packaged in various formats and very often some
Windows-only executable is used for unpacking files. These extractors
allow to deal with some of them without having to run the executables.
Change-Id: I1346807508a6baba801c4d5ed0a575b17e06c8d4
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83522
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M util/liveiso/nixos/common.nix
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nicholas Chin: Looks good to me, approved
diff --git a/util/liveiso/nixos/common.nix b/util/liveiso/nixos/common.nix
index d461976..4c906ca 100644
--- a/util/liveiso/nixos/common.nix
+++ b/util/liveiso/nixos/common.nix
@@ -104,6 +104,7 @@
acpica-tools
btrfs-progs
bzip2
+ cabextract
ccrypt
chipsec
coreboot-utils
@@ -130,6 +131,7 @@
hexdump
htop
i2c-tools
+ innoextract
intel-gpu-tools
inxi
iotools
@@ -169,6 +171,7 @@
tpm2-tools
uefitool
uefitoolPackages.old-engine
+ unshield
unzip
upterm
usbutils
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Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83495?usp=email )
Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/3c20a394_17122777?us… :
PS4, Line 16: cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);
> Also the issue is happening only in MonkeyIsland and not on Zork(prior generation) or Skyrim(later generation).
Cezanne seems to have the smallest PSP SRAM size allocated for verstage among all the AMD programs.
Picasso(Zork) - 160 KiB (116 KiB for text, data, bss + 44 KiB for stack)
Cezanne(Guybrush) - 148 KiB (108 KiB for text, data, bass + 40 KiB for stack)
Mendocino(Skyrim) - 208 KiB (168 KiB for text, data, bss + 40 KiB for stack)
That probably is the reason why we are facing this error in Cezanne.
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Julius Werner has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83503?usp=email )
Change subject: azalia: Get rid of "return {-1,0}
......................................................................
Patch Set 5:
(1 comment)
File src/device/azalia_device.c:
https://review.coreboot.org/c/coreboot/+/83503/comment/8bbada03_23cd4f54?us… :
PS5, Line 56: if (azalia_exit_reset(base) == CB_ERR)
You should still test cb_errs for failure with `< 0` or `!= CB_SUCCESS`, unless you're really only looking for one specific error code.
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